Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.40435144b4ea40b7af8f0997d341d8de.6 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-12T03:22:08 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=82
  • AGG_IO=82
  • AGG_SLICE=629
  • NUM_4_INPUT_LUT=941
  • NUM_BONDED_IBUF=40
  • NUM_BONDED_IOB=42
  • NUM_BUFGMUX=4
  • NUM_CYMUX=138
  • NUM_DCM=1
  • NUM_LUT_RT=62
  • NUM_RAMB16BWE=8
  • NUM_SLICEL=629
  • NUM_SLICE_FF=873
  • NUM_XOR=126
 		NetStatistics
  • NumNets_Active=1336
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=511
  • NumNodesOfType_Active_CNTRLPIN=503
  • NumNodesOfType_Active_DOUBLE=1825
  • NumNodesOfType_Active_DUMMY=2300
  • NumNodesOfType_Active_DUMMYBANK=11
  • NumNodesOfType_Active_DUMMYESC=48
  • NumNodesOfType_Active_GLOBAL=101
  • NumNodesOfType_Active_HFULLHEX=14
  • NumNodesOfType_Active_HLONG=4
  • NumNodesOfType_Active_HUNIHEX=68
  • NumNodesOfType_Active_INPUT=2642
  • NumNodesOfType_Active_IOBOUTPUT=48
  • NumNodesOfType_Active_OMUX=1415
  • NumNodesOfType_Active_OUTPUT=1197
  • NumNodesOfType_Active_PREBXBY=742
  • NumNodesOfType_Active_VFULLHEX=115
  • NumNodesOfType_Active_VLONG=23
  • NumNodesOfType_Active_VUNIHEX=108
  • NumNodesOfType_Vcc_BRAMDUMMY=40
  • NumNodesOfType_Vcc_CNTRLPIN=4
  • NumNodesOfType_Vcc_INPUT=60
  • NumNodesOfType_Vcc_PREBXBY=14
  • NumNodesOfType_Vcc_VCCOUT=49
 SiteStatistics
  • IBUF-DIFFMLR=6
  • IBUF-DIFFMTB=10
  • IBUF-DIFFSLR=10
  • IBUF-DIFFSTB=12
  • IOB-DIFFMLR=9
  • IOB-DIFFMTB=16
  • IOB-DIFFSLR=4
  • IOB-DIFFSTB=13
  • SLICEL-SLICEM=290
 		SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=1
  • DCM_DCM=1
  • IBUF=40
  • IBUF_DELAY_ADJ_BBOX=40
  • IBUF_INBUF=40
  • IBUF_PAD=40
  • IOB=42
  • IOB_DELAY_ADJ_BBOX=8
  • IOB_INBUF=8
  • IOB_OUTBUF=42
  • IOB_PAD=42
  • RAMB16BWE=8
  • RAMB16BWE_RAMB16BWE=8
  • SLICEL=629
  • SLICEL_C1VDD=32
  • SLICEL_C2VDD=30
  • SLICEL_CYMUXF=70
  • SLICEL_CYMUXG=68
  • SLICEL_F=464
  • SLICEL_F5MUX=15
  • SLICEL_FFX=452
  • SLICEL_FFY=421
  • SLICEL_G=477
  • SLICEL_GNDF=38
  • SLICEL_GNDG=38
  • SLICEL_XORF=64
  • SLICEL_XORG=62
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[9:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:40]
  • IBUF_DELAY_VALUE=[DLY0:40]
  • IFD_DELAY_VALUE=[DLY0:40]
  • SEL_IN=[SEL_IN:40] [SEL_IN_INV:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:40]
 IOB
  • O1=[O1_INV:0] [O1:42]
  • T1=[T1_INV:0] [T1:8]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:8]
  • IBUF_DELAY_VALUE=[DLY0:8]
  • IFD_DELAY_VALUE=[DLY0:8]
  • SEL_IN=[SEL_IN:8] [SEL_IN_INV:0]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:42]
  • SUSPEND=[3STATE:42]
  • TRI=[TRI_INV:0] [TRI:8]
 IOB_PAD
  • DRIVEATTRBOX=[12:42]
  • IOATTRBOX=[LVCMOS25:42]
  • SLEW=[SLOW:42]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:0] [WEB0_INV:8]
  • WEB1=[WEB1:0] [WEB1_INV:8]
  • WEB2=[WEB2_INV:8] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:8]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • DATA_WIDTH_A=[1:8]
  • DATA_WIDTH_B=[0:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:0] [WEB0_INV:8]
  • WEB1=[WEB1:0] [WEB1_INV:8]
  • WEB2=[WEB2_INV:8] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:8]
  • WRITE_MODE_A=[WRITE_FIRST:8]
  • WRITE_MODE_B=[WRITE_FIRST:8]
 SLICEL
  • BX=[BX_INV:3] [BX:143]
  • BY=[BY:141] [BY_INV:6]
  • CE=[CE:330] [CE_INV:34]
  • CIN=[CIN_INV:0] [CIN:68]
  • CLK=[CLK:449] [CLK_INV:52]
  • SR=[SR:122] [SR_INV:8]
 SLICEL_CYMUXF
  • 0=[0:70] [0_INV:0]
  • 1=[1_INV:0] [1:70]
 SLICEL_CYMUXG
  • 0=[0:68] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:15] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:304] [CE_INV:32]
  • CK=[CK:417] [CK_INV:35]
  • D=[D:449] [D_INV:3]
  • FFX_INIT_ATTR=[INIT0:447] [INIT1:5]
  • FFX_SR_ATTR=[SRLOW:450] [SRHIGH:2]
  • LATCH_OR_FF=[FF:452]
  • REV=[REV_INV:0] [REV:64]
  • SR=[SR:102] [SR_INV:8]
  • SYNC_ATTR=[ASYNC:452]
 SLICEL_FFY
  • CE=[CE:329] [CE_INV:32]
  • CK=[CK:371] [CK_INV:50]
  • D=[D:415] [D_INV:6]
  • FFY_INIT_ATTR=[INIT0:413] [INIT1:8]
  • FFY_SR_ATTR=[SRLOW:414] [SRHIGH:7]
  • LATCH_OR_FF=[FF:421]
  • SR=[SR:56] [SR_INV:8]
  • SYNC_ATTR=[ASYNC:406] [SYNC:15]
 SLICEL_XORF
  • 1=[1_INV:0] [1:64]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
 BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
 BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
 DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
 DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS2=1
 IBUF
  • I=40
  • PAD=40
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=40
  • SEL_IN=40
 IBUF_INBUF
  • IN=40
  • OUT=40
 IBUF_PAD
  • PAD=40
 IOB
  • I=8
  • O1=42
  • PAD=42
  • T1=8
 IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=8
  • SEL_IN=8
 IOB_INBUF
  • IN=8
  • OUT=8
 IOB_OUTBUF
  • IN=42
  • OUT=42
  • TRI=8
 IOB_PAD
  • PAD=42
 RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • CLKA=8
  • DOA0=8
  • ENA=8
  • SSRA=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 RAMB16BWE_RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • CLKA=8
  • DOA0=8
  • ENA=8
  • SSRA=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 SLICEL
  • BX=146
  • BY=147
  • CE=364
  • CIN=68
  • CLK=501
  • COUT=68
  • F1=464
  • F2=432
  • F3=182
  • F4=55
  • G1=477
  • G2=447
  • G3=182
  • G4=53
  • SR=130
  • X=133
  • XQ=452
  • Y=116
  • YQ=421
 SLICEL_C1VDD
  • 1=32
 SLICEL_C2VDD
  • 1=30
 SLICEL_CYMUXF
  • 0=70
  • 1=70
  • OUT=70
  • S0=70
 SLICEL_CYMUXG
  • 0=68
  • 1=68
  • OUT=68
  • S0=68
 SLICEL_F
  • A1=464
  • A2=432
  • A3=182
  • A4=55
  • D=464
 SLICEL_F5MUX
  • F=15
  • G=15
  • OUT=15
  • S0=15
 SLICEL_FFX
  • CE=336
  • CK=452
  • D=452
  • Q=452
  • REV=64
  • SR=110
 SLICEL_FFY
  • CE=361
  • CK=421
  • D=421
  • Q=421
  • SR=64
 SLICEL_G
  • A1=477
  • A2=447
  • A3=182
  • A4=53
  • D=477
 SLICEL_GNDF
  • 0=38
 SLICEL_GNDG
  • 0=38
 SLICEL_XORF
  • 0=64
  • 1=64
  • O=64
 SLICEL_XORG
  • 0=62
  • 1=62
  • O=62
 
Software Quality
Run Statistics
Bitgen 12939 12938 0 0 0 0 0
MAP 7055 6857 0 0 0 0 0
NGDBuild 7372 7356 0 0 0 0 0
PAR 6849 6497 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 75027 75023 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6503 6499 0 0 0 0 0
xst 7136 7033 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=12
NGDBUILD_NUM_FDCE=12 NGDBUILD_NUM_FDE=417 NGDBUILD_NUM_FDPE=3 NGDBUILD_NUM_FDR_1=12
NGDBUILD_NUM_FDSE=3 NGDBUILD_NUM_GND=8 NGDBUILD_NUM_IBUF=38 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=6 NGDBUILD_NUM_IOBUF=8 NGDBUILD_NUM_LUT2=357 NGDBUILD_NUM_LUT3=95
NGDBUILD_NUM_LUT3_L=4 NGDBUILD_NUM_LUT4=63 NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXF5=12
NGDBUILD_NUM_NAND2=4 NGDBUILD_NUM_OBUF=34 NGDBUILD_NUM_VCC=6
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=79 NGDBUILD_NUM_FDC=10
NGDBUILD_NUM_FDCE=76 NGDBUILD_NUM_FDCE_1=3 NGDBUILD_NUM_FDCP=64 NGDBUILD_NUM_FDC_1=5
NGDBUILD_NUM_FDE=611 NGDBUILD_NUM_FDP=6 NGDBUILD_NUM_FDPE=3 NGDBUILD_NUM_FDPE_1=1
NGDBUILD_NUM_FDR_1=12 NGDBUILD_NUM_FDSE=3 NGDBUILD_NUM_GND=13 NGDBUILD_NUM_IBUF=46
NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=12 NGDBUILD_NUM_LUT1_L=66 NGDBUILD_NUM_LUT2=491
NGDBUILD_NUM_LUT2_L=48 NGDBUILD_NUM_LUT3=106 NGDBUILD_NUM_LUT3_L=145 NGDBUILD_NUM_LUT4=92
NGDBUILD_NUM_LUT4_L=9 NGDBUILD_NUM_MUXCY=2 NGDBUILD_NUM_MUXCY_L=136 NGDBUILD_NUM_MUXF5=15
NGDBUILD_NUM_NAND2=4 NGDBUILD_NUM_OBUF=34 NGDBUILD_NUM_OBUFT=8 NGDBUILD_NUM_RAMB16BWE=8
NGDBUILD_NUM_VCC=9 NGDBUILD_NUM_XORCY=126