Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.592510907e62418c9fc35f632ef3304e.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T19:49:54 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=88
  • AGG_IO=88
  • AGG_SLICE=1326
  • NUM_4_INPUT_LUT=2414
  • NUM_BONDED_IBUF=51
  • NUM_BONDED_IOB=37
  • NUM_BUFGMUX=8
  • NUM_CARRY_SKIP=4
  • NUM_CYMUX=383
  • NUM_DCM=2
  • NUM_DP_RAM=64
  • NUM_IOB_FF=8
  • NUM_LUT_RT=109
  • NUM_MULTAND=9
  • NUM_RAMB16BWE=10
  • NUM_SHIFT=5
  • NUM_SLICEL=1275
  • NUM_SLICEM=51
  • NUM_SLICE_FF=764
  • NUM_XOR=352
 		NetStatistics
  • NumNets_Active=2749
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=140
  • NumNodesOfType_Active_BRAMDUMMY=84
  • NumNodesOfType_Active_CLKPIN=546
  • NumNodesOfType_Active_CNTRLPIN=749
  • NumNodesOfType_Active_DOUBLE=5511
  • NumNodesOfType_Active_DUMMY=7520
  • NumNodesOfType_Active_DUMMYBANK=126
  • NumNodesOfType_Active_DUMMYESC=24
  • NumNodesOfType_Active_GLOBAL=188
  • NumNodesOfType_Active_HFULLHEX=68
  • NumNodesOfType_Active_HLONG=4
  • NumNodesOfType_Active_HUNIHEX=294
  • NumNodesOfType_Active_INPUT=8284
  • NumNodesOfType_Active_IOBOUTPUT=31
  • NumNodesOfType_Active_OMUX=2396
  • NumNodesOfType_Active_OUTPUT=2614
  • NumNodesOfType_Active_PREBXBY=1929
  • NumNodesOfType_Active_VFULLHEX=284
  • NumNodesOfType_Active_VLONG=52
  • NumNodesOfType_Active_VUNIHEX=447
 SiteStatistics
  • IBUF-DIFFMLR=12
  • IBUF-DIFFMTB=13
  • IBUF-DIFFSLR=11
  • IBUF-DIFFSTB=13
  • IOB-DIFFMLR=3
  • IOB-DIFFMTB=15
  • IOB-DIFFSLR=4
  • IOB-DIFFSTB=15
  • SLICEL-SLICEM=579
 		SiteSummary
  • BUFGMUX=8
  • BUFGMUX_GCLKMUX=8
  • BUFGMUX_GCLK_BUFFER=8
  • DCM=2
  • DCM_DCM=2
  • IBUF=51
  • IBUF_DELAY_ADJ_BBOX=51
  • IBUF_IFF1=8
  • IBUF_INBUF=51
  • IBUF_PAD=51
  • IOB=37
  • IOB_OUTBUF=37
  • IOB_PAD=37
  • RAMB16BWE=10
  • RAMB16BWE_RAMB16BWE=10
  • SLICEL=1275
  • SLICEL_C1VDD=15
  • SLICEL_C2VDD=18
  • SLICEL_CYMUXF=202
  • SLICEL_CYMUXG=181
  • SLICEL_F=1172
  • SLICEL_F5MUX=152
  • SLICEL_F6MUX=9
  • SLICEL_FAND=4
  • SLICEL_FFX=398
  • SLICEL_FFY=345
  • SLICEL_G=1141
  • SLICEL_GAND=5
  • SLICEL_GNDF=131
  • SLICEL_GNDG=110
  • SLICEL_VDDG=4
  • SLICEL_XORF=184
  • SLICEL_XORG=168
  • SLICEM=51
  • SLICEM_F=50
  • SLICEM_F5MUX=16
  • SLICEM_F6MUX=16
  • SLICEM_FFX=2
  • SLICEM_FFY=19
  • SLICEM_G=51
  • SLICEM_WSGEN=35
 
Configuration Data
BUFGMUX
  • S=[S_INV:8] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:8]
  • S=[S_INV:8] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[5:1] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 IBUF
  • ICE=[ICE:8] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:8]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:51]
  • IBUF_DELAY_VALUE=[DLY0:51]
  • IFD_DELAY_VALUE=[DLY0:43] [DLY5:8]
  • SEL_IN=[SEL_IN:51] [SEL_IN_INV:0]
 IBUF_IFF1
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:8] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:8]
  • LATCH_OR_FF=[FF:8]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:51]
 IOB
  • O1=[O1_INV:3] [O1:34]
 IOB_OUTBUF
  • IN=[IN_INV:3] [IN:34]
  • SUSPEND=[3STATE:37]
 IOB_PAD
  • DRIVEATTRBOX=[12:37]
  • IOATTRBOX=[LVTTL:37]
  • SLEW=[SLOW:37]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:10]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:10]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:10]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA0=[WEA0:5] [WEA0_INV:5]
  • WEA1=[WEA1:5] [WEA1_INV:5]
  • WEA2=[WEA2:5] [WEA2_INV:5]
  • WEA3=[WEA3_INV:5] [WEA3:5]
  • WEB0=[WEB0:2] [WEB0_INV:8]
  • WEB1=[WEB1:2] [WEB1_INV:8]
  • WEB2=[WEB2_INV:8] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:8]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:10]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[2:4] [9:6]
  • DATA_WIDTH_B=[0:8] [9:2]
  • ENA=[ENA_INV:0] [ENA:10]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:10]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA0=[WEA0:5] [WEA0_INV:5]
  • WEA1=[WEA1:5] [WEA1_INV:5]
  • WEA2=[WEA2:5] [WEA2_INV:5]
  • WEA3=[WEA3_INV:5] [WEA3:5]
  • WEB0=[WEB0:2] [WEB0_INV:8]
  • WEB1=[WEB1:2] [WEB1_INV:8]
  • WEB2=[WEB2_INV:8] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:8]
  • WRITE_MODE_A=[WRITE_FIRST:10]
  • WRITE_MODE_B=[WRITE_FIRST:10]
 SLICEL
  • BX=[BX_INV:15] [BX:218]
  • BY=[BY:81] [BY_INV:10]
  • CE=[CE:405] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:177]
  • CLK=[CLK:483] [CLK_INV:4]
  • SR=[SR:91] [SR_INV:195]
 SLICEL_CYMUXF
  • 0=[0:202] [0_INV:0]
  • 1=[1_INV:9] [1:193]
 SLICEL_CYMUXG
  • 0=[0:177] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:152] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:9] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:350] [CE_INV:0]
  • CK=[CK:398] [CK_INV:0]
  • D=[D:392] [D_INV:6]
  • FFX_INIT_ATTR=[INIT0:369] [INIT1:29]
  • FFX_SR_ATTR=[SRLOW:369] [SRHIGH:29]
  • LATCH_OR_FF=[FF:398]
  • SR=[SR:68] [SR_INV:158]
  • SYNC_ATTR=[ASYNC:366] [SYNC:32]
 SLICEL_FFY
  • CE=[CE:277] [CE_INV:0]
  • CK=[CK:341] [CK_INV:4]
  • D=[D:335] [D_INV:10]
  • FFY_INIT_ATTR=[INIT0:329] [INIT1:16]
  • FFY_SR_ATTR=[SRLOW:329] [SRHIGH:16]
  • LATCH_OR_FF=[FF:345]
  • SR=[SR:83] [SR_INV:112]
  • SYNC_ATTR=[ASYNC:299] [SYNC:46]
 SLICEL_XORF
  • 1=[1_INV:9] [1:175]
 SLICEM
  • BX=[BX_INV:0] [BX:18]
  • BY=[BY:51] [BY_INV:0]
  • CE=[CE:16] [CE_INV:0]
  • CLK=[CLK:35] [CLK_INV:0]
  • SR=[SR:35] [SR_INV:0]
 SLICEM_F
  • DI=[DI:34] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:32] [SHIFT_REG:2]
  • LUT_OR_MEM=[LUT:16] [RAM:34]
 SLICEM_F5MUX
  • S0=[S0:16] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:16] [S0_INV:0]
 SLICEM_FFX
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:2]
  • FFX_SR_ATTR=[SRLOW:2]
  • LATCH_OR_FF=[FF:2]
  • SYNC_ATTR=[ASYNC:2]
 SLICEM_FFY
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:19] [CK_INV:0]
  • D=[D:19] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:19]
  • FFY_SR_ATTR=[SRLOW:19]
  • LATCH_OR_FF=[FF:19]
  • SYNC_ATTR=[ASYNC:19]
 SLICEM_G
  • DI=[DI:35] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:32] [SHIFT_REG:3]
  • LUT_OR_MEM=[LUT:16] [RAM:35]
 SLICEM_WSGEN
  • CK=[CK:35] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:19]
  • WE=[WE_INV:0] [WE:35]
 
Pin Data
BUFGMUX
  • I0=8
  • O=8
  • S=8
 BUFGMUX_GCLKMUX
  • I0=8
  • OUT=8
  • S=8
 BUFGMUX_GCLK_BUFFER
  • IN=8
  • OUT=8
 DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
 DCM_DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
 IBUF
  • I=43
  • ICE=8
  • ICLK1=8
  • IQ1=8
  • PAD=51
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=43
  • IFD_OUT=8
  • SEL_IN=51
 IBUF_IFF1
  • CE=8
  • CK=8
  • D=8
  • Q=8
 IBUF_INBUF
  • IN=51
  • OUT=51
 IBUF_PAD
  • PAD=51
 IOB
  • O1=37
  • PAD=37
 IOB_OUTBUF
  • IN=37
  • OUT=37
 IOB_PAD
  • PAD=37
 RAMB16BWE
  • ADDRA1=4
  • ADDRA10=10
  • ADDRA11=10
  • ADDRA12=10
  • ADDRA13=10
  • ADDRA2=4
  • ADDRA3=10
  • ADDRA4=10
  • ADDRA5=10
  • ADDRA6=10
  • ADDRA7=10
  • ADDRA8=10
  • ADDRA9=10
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=10
  • CLKB=2
  • DIA0=6
  • DIA1=6
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIPA0=2
  • DOA0=8
  • DOA1=8
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOB0=2
  • DOB1=2
  • DOB2=2
  • ENA=10
  • ENB=2
  • SSRA=10
  • SSRB=2
  • WEA0=10
  • WEA1=10
  • WEA2=10
  • WEA3=10
  • WEB0=10
  • WEB1=10
  • WEB2=10
  • WEB3=10
 RAMB16BWE_RAMB16BWE
  • ADDRA1=4
  • ADDRA10=10
  • ADDRA11=10
  • ADDRA12=10
  • ADDRA13=10
  • ADDRA2=4
  • ADDRA3=10
  • ADDRA4=10
  • ADDRA5=10
  • ADDRA6=10
  • ADDRA7=10
  • ADDRA8=10
  • ADDRA9=10
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=10
  • CLKB=2
  • DIA0=6
  • DIA1=6
  • DIA2=2
  • DIA3=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIPA0=2
  • DOA0=8
  • DOA1=8
  • DOA2=4
  • DOA3=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOB0=2
  • DOB1=2
  • DOB2=2
  • ENA=10
  • ENB=2
  • SSRA=10
  • SSRB=2
  • WEA0=10
  • WEA1=10
  • WEA2=10
  • WEA3=10
  • WEB0=10
  • WEB1=10
  • WEB2=10
  • WEB3=10
 SLICEL
  • BX=233
  • BY=91
  • CE=405
  • CIN=177
  • CLK=487
  • COUT=181
  • F1=1168
  • F2=1096
  • F3=848
  • F4=594
  • F5=18
  • FX=8
  • FXINA=9
  • FXINB=9
  • G1=1136
  • G2=1072
  • G3=826
  • G4=513
  • SR=286
  • X=776
  • XB=6
  • XQ=398
  • Y=714
  • YQ=345
 SLICEL_C1VDD
  • 1=15
 SLICEL_C2VDD
  • 1=18
 SLICEL_CYMUXF
  • 0=202
  • 1=202
  • OUT=202
  • S0=202
 SLICEL_CYMUXG
  • 0=177
  • 1=181
  • OUT=181
  • S0=181
 SLICEL_F
  • A1=1166
  • A2=1096
  • A3=848
  • A4=594
  • D=1172
 SLICEL_F5MUX
  • F=152
  • G=152
  • OUT=152
  • S0=152
 SLICEL_F6MUX
  • 0=9
  • 1=9
  • OUT=9
  • S0=9
 SLICEL_FAND
  • 0=4
  • 1=4
  • O=4
 SLICEL_FFX
  • CE=350
  • CK=398
  • D=398
  • Q=398
  • SR=226
 SLICEL_FFY
  • CE=277
  • CK=345
  • D=345
  • Q=345
  • SR=195
 SLICEL_G
  • A1=1132
  • A2=1072
  • A3=826
  • A4=513
  • D=1141
 SLICEL_GAND
  • 0=5
  • 1=5
  • O=5
 SLICEL_GNDF
  • 0=131
 SLICEL_GNDG
  • 0=110
 SLICEL_VDDG
  • 1=4
 SLICEL_XORF
  • 0=184
  • 1=184
  • O=184
 SLICEL_XORG
  • 0=168
  • 1=168
  • O=168
 SLICEM
  • BX=18
  • BY=51
  • CE=16
  • CLK=35
  • F1=50
  • F2=50
  • F3=50
  • F4=39
  • F5=16
  • FX=8
  • FXINA=16
  • FXINB=16
  • G1=51
  • G2=51
  • G3=51
  • G4=46
  • SR=35
  • X=32
  • XQ=2
  • Y=24
  • YQ=19
 SLICEM_F
  • A1=50
  • A2=50
  • A3=50
  • A4=39
  • D=50
  • DI=34
  • WF1=32
  • WF2=32
  • WF3=32
  • WF4=32
  • WS=34
 SLICEM_F5MUX
  • F=16
  • G=16
  • OUT=16
  • S0=16
 SLICEM_F6MUX
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
 SLICEM_FFX
  • CK=2
  • D=2
  • Q=2
 SLICEM_FFY
  • CE=16
  • CK=19
  • D=19
  • Q=19
 SLICEM_G
  • A1=51
  • A2=51
  • A3=51
  • A4=46
  • D=35
  • DI=35
  • WG1=32
  • WG2=32
  • WG3=32
  • WG4=32
  • WS=35
 SLICEM_WSGEN
  • CK=35
  • WE=35
  • WSF=34
  • WSG=35
 
Software Quality
Run Statistics
Bitgen 12885 12884 0 0 0 0 0
MAP 7028 6830 0 0 0 0 0
NGDBuild 7345 7329 0 0 0 0 0
PAR 6822 6470 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74496 74492 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6476 6472 0 0 0 0 0
xst 7088 6985 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_BUF=3 NGDBUILD_NUM_BUFG=7 NGDBUILD_NUM_BUFGP=1
NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=29 NGDBUILD_NUM_FDC=39
NGDBUILD_NUM_FDCE=264 NGDBUILD_NUM_FDE=313 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=38
NGDBUILD_NUM_FDR=38 NGDBUILD_NUM_FDRE=31 NGDBUILD_NUM_FDR_1=4 NGDBUILD_NUM_FDSE=5
NGDBUILD_NUM_GND=22 NGDBUILD_NUM_IBUF=27 NGDBUILD_NUM_IBUFG=3 NGDBUILD_NUM_INV=73
NGDBUILD_NUM_LUT1=89 NGDBUILD_NUM_LUT2=351 NGDBUILD_NUM_LUT2_D=20 NGDBUILD_NUM_LUT2_L=21
NGDBUILD_NUM_LUT3=626 NGDBUILD_NUM_LUT3_D=52 NGDBUILD_NUM_LUT3_L=20 NGDBUILD_NUM_LUT4=937
NGDBUILD_NUM_LUT4_D=50 NGDBUILD_NUM_LUT4_L=124 NGDBUILD_NUM_MULT_AND=9 NGDBUILD_NUM_MUXCY=365
NGDBUILD_NUM_MUXF5=168 NGDBUILD_NUM_MUXF6=17 NGDBUILD_NUM_MUXF7=8 NGDBUILD_NUM_OBUF=37
NGDBUILD_NUM_RAM16X1D=32 NGDBUILD_NUM_RAMB16BWE=10 NGDBUILD_NUM_SRL16=5 NGDBUILD_NUM_VCC=16
NGDBUILD_NUM_XORCY=345
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_BUF=3 NGDBUILD_NUM_BUFG=8 NGDBUILD_NUM_DCM_SP=2
NGDBUILD_NUM_FD=38 NGDBUILD_NUM_FDC=39 NGDBUILD_NUM_FDCE=264 NGDBUILD_NUM_FDE=313
NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=38 NGDBUILD_NUM_FDR=38 NGDBUILD_NUM_FDRE=31
NGDBUILD_NUM_FDR_1=4 NGDBUILD_NUM_FDSE=5 NGDBUILD_NUM_GND=23 NGDBUILD_NUM_IBUF=47
NGDBUILD_NUM_IBUFG=4 NGDBUILD_NUM_INV=74 NGDBUILD_NUM_LUT1=89 NGDBUILD_NUM_LUT1_L=8
NGDBUILD_NUM_LUT2=359 NGDBUILD_NUM_LUT2_D=20 NGDBUILD_NUM_LUT2_L=21 NGDBUILD_NUM_LUT3=626
NGDBUILD_NUM_LUT3_D=52 NGDBUILD_NUM_LUT3_L=20 NGDBUILD_NUM_LUT4=941 NGDBUILD_NUM_LUT4_D=50
NGDBUILD_NUM_LUT4_L=125 NGDBUILD_NUM_MULT_AND=9 NGDBUILD_NUM_MUXCY=366 NGDBUILD_NUM_MUXCY_L=14
NGDBUILD_NUM_MUXF5=168 NGDBUILD_NUM_MUXF6=17 NGDBUILD_NUM_MUXF7=8 NGDBUILD_NUM_OBUF=37
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