BUFGMUX
BUFGMUX_GCLKMUX
- DISABLE_ATTR=[LOW:7]
- S=[S_INV:7] [S:0]
DCM
- PSCLK=[PSCLK_INV:0] [PSCLK:2]
- PSEN=[PSEN_INV:0] [PSEN:2]
- PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
- RST=[RST:1] [RST_INV:1]
DCM_DCM
- CLKDV_DIVIDE=[2:1] [16:1]
- CLKOUT_PHASE_SHIFT=[NONE:2]
- CLK_FEEDBACK=[1X:2]
- DESKEW_ADJUST=[9:2]
- DFS_FREQUENCY_MODE=[LOW:2]
- DLL_FREQUENCY_MODE=[LOW:2]
- DUTY_CYCLE_CORRECTION=[TRUE:2]
- FACTORY_JF1=[0XC0:2]
- FACTORY_JF2=[0X80:2]
- PSCLK=[PSCLK_INV:0] [PSCLK:2]
- PSEN=[PSEN_INV:0] [PSEN:2]
- PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
- RST=[RST:1] [RST_INV:1]
IBUF
- ICE=[ICE:8] [ICE_INV:0]
- ICLK1=[ICLK1_INV:0] [ICLK1:9]
IBUF_DELAY_ADJ_BBOX
- DELAY_ADJ_ATTRBOX=[FIXED:49]
- IBUF_DELAY_VALUE=[DLY0:49]
- IFD_DELAY_VALUE=[DLY0:40] [DLY5:9]
- SEL_IN=[SEL_IN:49] [SEL_IN_INV:0]
IBUF_IFF1
- CE=[CE:8] [CE_INV:0]
- CK=[CK:9] [CK_INV:0]
- IFF1_INIT_ATTR=[INIT0:9]
- LATCH_OR_FF=[FF:9]
IBUF_PAD
- IOATTRBOX=[LVTTL:49]
- PULL=[PULLUP:1]
IOB
IOB_OUTBUF
- IN=[IN_INV:1] [IN:36]
- SUSPEND=[3STATE:37]
IOB_PAD
- DRIVEATTRBOX=[12:37]
- IOATTRBOX=[LVTTL:37]
- SLEW=[SLOW:37]
|
MULT18X18SIO
- CEA=[CEA_INV:0] [CEA:2]
- CEB=[CEB_INV:0] [CEB:2]
- CEP=[CEP:2] [CEP_INV:0]
- CLK=[CLK:2] [CLK_INV:0]
- RSTA=[RSTA:2] [RSTA_INV:0]
- RSTB=[RSTB:2] [RSTB_INV:0]
- RSTP=[RSTP_INV:0] [RSTP:2]
MULT18X18SIO_MULT18X18SIO
- AREG=[0:2]
- BREG=[0:2]
- B_INPUT=[DIRECT:2]
- CEA=[CEA_INV:0] [CEA:2]
- CEB=[CEB_INV:0] [CEB:2]
- CEP=[CEP:2] [CEP_INV:0]
- CLK=[CLK:2] [CLK_INV:0]
- PREG=[0:2]
- PREG_CLKINVERSION=[0:2]
- RSTA=[RSTA:2] [RSTA_INV:0]
- RSTB=[RSTB:2] [RSTB_INV:0]
- RSTP=[RSTP_INV:0] [RSTP:2]
RAMB16BWE
- CLKA=[CLKA_INV:0] [CLKA:19]
- CLKB=[CLKB_INV:0] [CLKB:2]
- ENA=[ENA_INV:0] [ENA:19]
- ENB=[ENB_INV:0] [ENB:2]
- SSRA=[SSRA_INV:0] [SSRA:19]
- SSRB=[SSRB_INV:0] [SSRB:2]
- WEA0=[WEA0:17] [WEA0_INV:2]
- WEA1=[WEA1:17] [WEA1_INV:2]
- WEA2=[WEA2:17] [WEA2_INV:2]
- WEA3=[WEA3_INV:2] [WEA3:17]
- WEB0=[WEB0:2] [WEB0_INV:17]
- WEB1=[WEB1:2] [WEB1_INV:17]
- WEB2=[WEB2_INV:17] [WEB2:2]
- WEB3=[WEB3:2] [WEB3_INV:17]
RAMB16BWE_RAMB16BWE
- CLKA=[CLKA_INV:0] [CLKA:19]
- CLKB=[CLKB_INV:0] [CLKB:2]
- DATA_WIDTH_A=[4:8] [9:10] [18:1]
- DATA_WIDTH_B=[0:17] [9:1] [18:1]
- ENA=[ENA_INV:0] [ENA:19]
- ENB=[ENB_INV:0] [ENB:2]
- SSRA=[SSRA_INV:0] [SSRA:19]
- SSRB=[SSRB_INV:0] [SSRB:2]
- WEA0=[WEA0:17] [WEA0_INV:2]
- WEA1=[WEA1:17] [WEA1_INV:2]
- WEA2=[WEA2:17] [WEA2_INV:2]
- WEA3=[WEA3_INV:2] [WEA3:17]
- WEB0=[WEB0:2] [WEB0_INV:17]
- WEB1=[WEB1:2] [WEB1_INV:17]
- WEB2=[WEB2_INV:17] [WEB2:2]
- WEB3=[WEB3:2] [WEB3_INV:17]
- WRITE_MODE_A=[WRITE_FIRST:19]
- WRITE_MODE_B=[WRITE_FIRST:19]
|
SLICEL
- BX=[BX_INV:18] [BX:943]
- BY=[BY:451] [BY_INV:29]
- CE=[CE:1151] [CE_INV:35]
- CIN=[CIN_INV:0] [CIN:451]
- CLK=[CLK:1340] [CLK_INV:10]
- SR=[SR:806] [SR_INV:20]
SLICEL_CYMUXF
- 0=[0:511] [0_INV:0]
- 1=[1_INV:3] [1:508]
SLICEL_CYMUXG
SLICEL_F5MUX
SLICEL_F6MUX
SLICEL_FFX
- CE=[CE:992] [CE_INV:32]
- CK=[CK:1166] [CK_INV:3]
- D=[D:1154] [D_INV:15]
- FFX_INIT_ATTR=[INIT0:1057] [INIT1:112]
- FFX_SR_ATTR=[SRLOW:1064] [SRHIGH:105]
- LATCH_OR_FF=[FF:1169]
- REV=[REV_INV:0] [REV:68]
- SR=[SR:708] [SR_INV:16]
- SYNC_ATTR=[ASYNC:1056] [SYNC:113]
SLICEL_FFY
- CE=[CE:816] [CE_INV:33]
- CK=[CK:927] [CK_INV:10]
- D=[D:908] [D_INV:29]
- FFY_INIT_ATTR=[INIT0:886] [INIT1:51]
- FFY_SR_ATTR=[SRLOW:889] [SRHIGH:48]
- LATCH_OR_FF=[FF:937]
- REV=[REV_INV:0] [REV:8]
- SR=[SR:509] [SR_INV:20]
- SYNC_ATTR=[ASYNC:814] [SYNC:123]
SLICEL_XORF
SLICEM
- BX=[BX_INV:0] [BX:38]
- BY=[BY:110] [BY_INV:0]
- CE=[CE:46] [CE_INV:0]
- CLK=[CLK:78] [CLK_INV:0]
- SR=[SR:78] [SR_INV:0]
SLICEM_F
- DI=[DI:70] [DI_INV:0]
- F_ATTR=[DUAL_PORT:64] [SHIFT_REG:6]
- LUT_OR_MEM=[LUT:32] [RAM:70]
|
SLICEM_F5MUX
SLICEM_F6MUX
SLICEM_FFX
- CE=[CE:6] [CE_INV:0]
- CK=[CK:6] [CK_INV:0]
- D=[D:6] [D_INV:0]
- FFX_INIT_ATTR=[INIT0:6]
- FFX_SR_ATTR=[SRLOW:6]
- LATCH_OR_FF=[FF:6]
- SYNC_ATTR=[ASYNC:6]
SLICEM_FFY
- CE=[CE:46] [CE_INV:0]
- CK=[CK:46] [CK_INV:0]
- D=[D:46] [D_INV:0]
- FFY_INIT_ATTR=[INIT0:46]
- FFY_SR_ATTR=[SRLOW:46]
- LATCH_OR_FF=[FF:46]
- SYNC_ATTR=[ASYNC:46]
SLICEM_G
- DI=[DI:78] [DI_INV:0]
- G_ATTR=[DUAL_PORT:64] [SHIFT_REG:14]
- LUT_OR_MEM=[LUT:32] [RAM:78]
SLICEM_WSGEN
- CK=[CK:78] [CK_INV:0]
- SYNC_ATTR=[ASYNC:46]
- WE=[WE_INV:0] [WE:78]
|