Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.c6e1bf3459474daba571949c5e631456.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T19:58:47 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=50
  • AGG_IO=50
  • AGG_SLICE=3112
  • NUM_4_INPUT_LUT=5163
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=46
  • NUM_BUFGMUX=8
  • NUM_CYMUX=831
  • NUM_DCM=3
  • NUM_DP_RAM=306
  • NUM_IOB_FF=70
  • NUM_LUT_RT=331
  • NUM_MULT18X18SIO=2
  • NUM_MULTAND=39
  • NUM_RAMB16BWE=8
  • NUM_SLICEL=2959
  • NUM_SLICEM=153
  • NUM_SLICE_FF=2512
  • NUM_XOR=770
 		NetStatistics
  • NumNets_Active=6321
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=192
  • NumNodesOfType_Active_BRAMDUMMY=232
  • NumNodesOfType_Active_CLKPIN=1787
  • NumNodesOfType_Active_CNTRLPIN=2738
  • NumNodesOfType_Active_DOUBLE=17169
  • NumNodesOfType_Active_DUMMY=16106
  • NumNodesOfType_Active_DUMMYBANK=159
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_GLOBAL=280
  • NumNodesOfType_Active_HFULLHEX=332
  • NumNodesOfType_Active_HLONG=77
  • NumNodesOfType_Active_HUNIHEX=1827
  • NumNodesOfType_Active_INPUT=18066
  • NumNodesOfType_Active_IOBOUTPUT=20
  • NumNodesOfType_Active_OMUX=5599
  • NumNodesOfType_Active_OUTPUT=6168
  • NumNodesOfType_Active_PREBXBY=4631
  • NumNodesOfType_Active_VFULLHEX=1293
  • NumNodesOfType_Active_VLONG=321
  • NumNodesOfType_Active_VUNIHEX=1936
  • NumNodesOfType_Gnd_BRAMDUMMY=82
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_DOUBLE=60
  • NumNodesOfType_Gnd_DUMMY=127
  • NumNodesOfType_Gnd_DUMMYBANK=7
  • NumNodesOfType_Gnd_INPUT=254
  • NumNodesOfType_Gnd_OMUX=100
  • NumNodesOfType_Gnd_OUTPUT=55
  • NumNodesOfType_Gnd_PREBXBY=46
  • NumNodesOfType_Gnd_VFULLHEX=4
  • NumNodesOfType_Gnd_VUNIHEX=2
 SiteStatistics
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSTB=2
  • IOB-DIFFMLR=20
  • IOB-DIFFMTB=4
  • IOB-DIFFSLR=19
  • IOB-DIFFSTB=3
  • SLICEL-SLICEM=1366
 		SiteSummary
  • BUFGMUX=8
  • BUFGMUX_GCLKMUX=8
  • BUFGMUX_GCLK_BUFFER=8
  • DCM=3
  • DCM_DCM=3
  • IBUF=4
  • IBUF_DELAY_ADJ_BBOX=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=46
  • IOB_DELAY_ADJ_BBOX=16
  • IOB_IFF1=16
  • IOB_INBUF=16
  • IOB_OFF1=38
  • IOB_OUTBUF=46
  • IOB_PAD=46
  • IOB_TFF1=16
  • MULT18X18SIO=2
  • MULT18X18SIO_MULT18X18SIO=2
  • RAMB16BWE=8
  • RAMB16BWE_RAMB16BWE=8
  • SLICEL=2959
  • SLICEL_C1VDD=17
  • SLICEL_C2VDD=14
  • SLICEL_CYMUXF=424
  • SLICEL_CYMUXG=407
  • SLICEL_F=2458
  • SLICEL_F5MUX=260
  • SLICEL_F6MUX=5
  • SLICEL_FAND=20
  • SLICEL_FFX=1374
  • SLICEL_FFY=1113
  • SLICEL_G=2399
  • SLICEL_GAND=19
  • SLICEL_GNDF=265
  • SLICEL_GNDG=255
  • SLICEL_XORF=387
  • SLICEL_XORG=383
  • SLICEM=153
  • SLICEM_F=153
  • SLICEM_FFX=25
  • SLICEM_G=153
  • SLICEM_WSGEN=153
 
Configuration Data
BUFGMUX
  • S=[S_INV:8] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:8]
  • S=[S_INV:8] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:2] [PSCLK:1]
  • PSEN=[PSEN_INV:2] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:2] [PSINCDEC:1]
  • RST=[RST:3] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2:2] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:3]
  • CLK_FEEDBACK=[1X:3]
  • DESKEW_ADJUST=[9:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • FACTORY_JF1=[0XC0:3]
  • FACTORY_JF2=[0X80:3]
  • PSCLK=[PSCLK_INV:2] [PSCLK:1]
  • PSEN=[PSEN_INV:2] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:2] [PSINCDEC:1]
  • RST=[RST:3] [RST_INV:0]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:4]
  • IBUF_DELAY_VALUE=[DLY0:4]
  • IFD_DELAY_VALUE=[DLY0:4]
  • SEL_IN=[SEL_IN:4] [SEL_IN_INV:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:4]
 IOB
  • ICE=[ICE:16] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:16]
  • O1=[O1_INV:0] [O1:46]
  • OCE=[OCE:0] [OCE_INV:15]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:38]
  • SR=[SR:37] [SR_INV:0]
  • T1=[T1_INV:0] [T1:16]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:16]
  • IBUF_DELAY_VALUE=[DLY0:16]
  • IFD_DELAY_VALUE=[DLY5:16]
  • SEL_IN=[SEL_IN:16] [SEL_IN_INV:0]
 IOB_IFF1
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:16]
  • IFF1_SR_ATTR=[SRLOW:16]
  • IFFATTRBOX=[SYNC:16]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:16] [SR_INV:0]
 IOB_OFF1
  • CE=[CE:0] [CE_INV:15]
  • CK=[CK:38] [CK_INV:0]
  • D=[D:38] [D_INV:0]
  • LATCH_OR_FF=[FF:38]
  • OFF1_INIT_ATTR=[INIT0:1] [INIT1:37]
  • OFF1_SR_ATTR=[SRHIGH:37]
  • OFFATTRBOX=[SYNC:37]
  • SR=[SR:37] [SR_INV:0]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:46]
  • SUSPEND=[3STATE:46]
  • TRI=[TRI_INV:0] [TRI:16]
 IOB_PAD
  • DRIVEATTRBOX=[12:46]
  • IOATTRBOX=[LVCMOS25:46]
  • SLEW=[SLOW:46]
 IOB_TFF1
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:16] [SR_INV:0]
  • TFF1_INIT_ATTR=[INIT1:16]
  • TFF1_SR_ATTR=[SRHIGH:16]
  • TFFATTRBOX=[SYNC:16]
 MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 MULT18X18SIO_MULT18X18SIO
  • AREG=[1:2]
  • BREG=[1:2]
  • B_INPUT=[DIRECT:2]
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • PREG=[0:2]
  • PREG_CLKINVERSION=[0:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • DATA_WIDTH_A=[4:8]
  • DATA_WIDTH_B=[4:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:8]
  • WRITE_MODE_B=[WRITE_FIRST:8]
 SLICEL
  • BX=[BX_INV:1] [BX:660]
  • BY=[BY:465] [BY_INV:9]
  • CE=[CE:1083] [CE_INV:14]
  • CIN=[CIN_INV:0] [CIN:404]
  • CLK=[CLK:1553] [CLK_INV:3]
  • SR=[SR:1376] [SR_INV:27]
 SLICEL_CYMUXF
  • 0=[0:424] [0_INV:0]
  • 1=[1_INV:1] [1:423]
 SLICEL_CYMUXG
  • 0=[0:407] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:260] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:5] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:977] [CE_INV:11]
  • CK=[CK:1373] [CK_INV:1]
  • D=[D:1374] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1329] [INIT1:45]
  • FFX_SR_ATTR=[SRLOW:1335] [SRHIGH:39]
  • LATCH_OR_FF=[FF:1374]
  • REV=[REV_INV:0] [REV:3]
  • SR=[SR:1219] [SR_INV:16]
  • SYNC_ATTR=[ASYNC:295] [SYNC:1079]
 SLICEL_FFY
  • CE=[CE:832] [CE_INV:12]
  • CK=[CK:1110] [CK_INV:3]
  • D=[D:1104] [D_INV:9]
  • FFY_INIT_ATTR=[INIT0:1050] [INIT1:63]
  • FFY_SR_ATTR=[SRLOW:1054] [SRHIGH:59]
  • LATCH_OR_FF=[FF:1113]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:975] [SR_INV:20]
  • SYNC_ATTR=[ASYNC:249] [SYNC:864]
 SLICEL_XORF
  • 1=[1_INV:1] [1:386]
 SLICEM
  • BY=[BY:153] [BY_INV:0]
  • CLK=[CLK:153] [CLK_INV:0]
  • SR=[SR:153] [SR_INV:0]
 SLICEM_F
  • DI=[DI:153] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:153]
  • LUT_OR_MEM=[RAM:153]
 SLICEM_FFX
  • CK=[CK:25] [CK_INV:0]
  • D=[D:25] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:25]
  • FFX_SR_ATTR=[SRLOW:25]
  • LATCH_OR_FF=[FF:25]
  • SYNC_ATTR=[ASYNC:25]
 SLICEM_G
  • DI=[DI:153] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:153]
  • LUT_OR_MEM=[RAM:153]
 SLICEM_WSGEN
  • CK=[CK:153] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:25]
  • WE=[WE_INV:0] [WE:153]
 
Pin Data
BUFGMUX
  • I0=8
  • O=8
  • S=8
 BUFGMUX_GCLKMUX
  • I0=8
  • OUT=8
  • S=8
 BUFGMUX_GCLK_BUFFER
  • IN=8
  • OUT=8
 DCM
  • CLK0=3
  • CLKDV=1
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
 DCM_DCM
  • CLK0=3
  • CLKDV=1
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
 IBUF
  • I=4
  • PAD=4
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • SEL_IN=4
 IBUF_INBUF
  • IN=4
  • OUT=4
 IBUF_PAD
  • PAD=4
 IOB
  • ICE=16
  • ICLK1=16
  • IQ1=16
  • O1=46
  • OCE=15
  • OTCLK1=38
  • PAD=46
  • SR=37
  • T1=16
 IOB_DELAY_ADJ_BBOX
  • IFD_OUT=16
  • SEL_IN=16
 IOB_IFF1
  • CE=16
  • CK=16
  • D=16
  • Q=16
  • SR=16
 IOB_INBUF
  • IN=16
  • OUT=16
 IOB_OFF1
  • CE=15
  • CK=38
  • D=38
  • Q=38
  • SR=37
 IOB_OUTBUF
  • IN=46
  • OUT=46
  • TRI=16
 IOB_PAD
  • PAD=46
 IOB_TFF1
  • CK=16
  • D=16
  • Q=16
  • SR=16
 MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 MULT18X18SIO_MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOA0=8
  • DOA1=8
  • DOA2=8
  • DOA3=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 RAMB16BWE_RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOA0=8
  • DOA1=8
  • DOA2=8
  • DOA3=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 SLICEL
  • BX=661
  • BY=474
  • CE=1097
  • CIN=404
  • CLK=1556
  • COUT=407
  • F1=2458
  • F2=2239
  • F3=1843
  • F4=996
  • F5=10
  • FXINA=5
  • FXINB=5
  • G1=2399
  • G2=2191
  • G3=1804
  • G4=1021
  • SR=1403
  • X=1503
  • XQ=1374
  • Y=1545
  • YQ=1113
 SLICEL_C1VDD
  • 1=17
 SLICEL_C2VDD
  • 1=14
 SLICEL_CYMUXF
  • 0=424
  • 1=424
  • OUT=424
  • S0=424
 SLICEL_CYMUXG
  • 0=407
  • 1=407
  • OUT=407
  • S0=407
 SLICEL_F
  • A1=2450
  • A2=2239
  • A3=1843
  • A4=996
  • D=2458
 SLICEL_F5MUX
  • F=260
  • G=260
  • OUT=260
  • S0=260
 SLICEL_F6MUX
  • 0=5
  • 1=5
  • OUT=5
  • S0=5
 SLICEL_FAND
  • 0=20
  • 1=20
  • O=20
 SLICEL_FFX
  • CE=988
  • CK=1374
  • D=1374
  • Q=1374
  • REV=3
  • SR=1235
 SLICEL_FFY
  • CE=844
  • CK=1113
  • D=1113
  • Q=1113
  • REV=1
  • SR=995
 SLICEL_G
  • A1=2390
  • A2=2189
  • A3=1804
  • A4=1021
  • D=2399
 SLICEL_GAND
  • 0=19
  • 1=19
  • O=19
 SLICEL_GNDF
  • 0=265
 SLICEL_GNDG
  • 0=255
 SLICEL_XORF
  • 0=387
  • 1=387
  • O=387
 SLICEL_XORG
  • 0=383
  • 1=383
  • O=383
 SLICEM
  • BY=153
  • CLK=153
  • F1=153
  • F2=153
  • F3=153
  • F4=153
  • G1=153
  • G2=153
  • G3=153
  • G4=153
  • SR=153
  • X=128
  • XQ=25
  • Y=23
 SLICEM_F
  • A1=153
  • A2=153
  • A3=153
  • A4=153
  • D=153
  • DI=153
  • WF1=153
  • WF2=153
  • WF3=153
  • WF4=153
  • WS=153
 SLICEM_FFX
  • CK=25
  • D=25
  • Q=25
 SLICEM_G
  • A1=153
  • A2=153
  • A3=153
  • A4=153
  • D=23
  • DI=153
  • WG1=153
  • WG2=153
  • WG3=153
  • WG4=153
  • WS=153
 SLICEM_WSGEN
  • CK=153
  • WE=153
  • WSF=153
  • WSG=153
 
Software Quality
Run Statistics
Bitgen 12887 12886 0 0 0 0 0
MAP 7029 6831 0 0 0 0 0
NGDBuild 7346 7330 0 0 0 0 0
PAR 6823 6471 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74510 74506 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6477 6473 0 0 0 0 0
xst 7089 6986 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUF=5 NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=49
NGDBUILD_NUM_FDC=111 NGDBUILD_NUM_FDCE=156 NGDBUILD_NUM_FDE=8 NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDR=75 NGDBUILD_NUM_FDRE=32 NGDBUILD_NUM_GND=13 NGDBUILD_NUM_IBUF=3
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=20 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT1=35
NGDBUILD_NUM_LUT2=184 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=106 NGDBUILD_NUM_LUT3_L=1
NGDBUILD_NUM_LUT4=219 NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_LUT4_L=21 NGDBUILD_NUM_MUXCY=120
NGDBUILD_NUM_MUXF5=2 NGDBUILD_NUM_NAND3=1 NGDBUILD_NUM_OBUF=30 NGDBUILD_NUM_RAM16X1D=25
NGDBUILD_NUM_VCC=8 NGDBUILD_NUM_XORCY=124
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=8 NGDBUILD_NUM_BUF=5 NGDBUILD_NUM_BUFG=8 NGDBUILD_NUM_DCM_SP=3
NGDBUILD_NUM_FD=62 NGDBUILD_NUM_FDC=114 NGDBUILD_NUM_FDCE=211 NGDBUILD_NUM_FDCPE=1
NGDBUILD_NUM_FDC_1=4 NGDBUILD_NUM_FDE=168 NGDBUILD_NUM_FDP=9 NGDBUILD_NUM_FDPE=3
NGDBUILD_NUM_FDR=475 NGDBUILD_NUM_FDRE=1490 NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDRSE=3
NGDBUILD_NUM_FDS=95 NGDBUILD_NUM_FDSE=59 NGDBUILD_NUM_GND=34 NGDBUILD_NUM_IBUF=19
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=37 NGDBUILD_NUM_LUT1=207 NGDBUILD_NUM_LUT1_L=177
NGDBUILD_NUM_LUT2=699 NGDBUILD_NUM_LUT2_L=197 NGDBUILD_NUM_LUT3=1081 NGDBUILD_NUM_LUT3_L=744
NGDBUILD_NUM_LUT4=1470 NGDBUILD_NUM_LUT4_D=2 NGDBUILD_NUM_LUT4_L=625 NGDBUILD_NUM_MULT18X18SIO=2
NGDBUILD_NUM_MULT_AND=39 NGDBUILD_NUM_MUXCY=124 NGDBUILD_NUM_MUXCY_L=707 NGDBUILD_NUM_MUXF5=269
NGDBUILD_NUM_MUXF6=5 NGDBUILD_NUM_NAND3=1 NGDBUILD_NUM_OBUF=30 NGDBUILD_NUM_OBUFT=16
NGDBUILD_NUM_RAMB16BWE=8 NGDBUILD_NUM_VCC=20 NGDBUILD_NUM_XORCY=770