Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.71aefb1bba904ef48f53dbb7b5e1fbd7.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-12T01:20:06 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=114
  • AGG_IO=114
  • AGG_SLICE=793
  • NUM_4_INPUT_LUT=1258
  • NUM_BONDED_IBUF=36
  • NUM_BONDED_IOB=78
  • NUM_BUFGMUX=6
  • NUM_CYMUX=63
  • NUM_DCM=2
  • NUM_DP_RAM=156
  • NUM_LUT_RT=68
  • NUM_RAMB16BWE=12
  • NUM_SHIFT=2
  • NUM_SLICEL=713
  • NUM_SLICEM=80
  • NUM_SLICE_FF=522
  • NUM_XOR=44
 		NetStatistics
  • NumNets_Active=1578
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=299
  • NumNodesOfType_Active_BRAMDUMMY=108
  • NumNodesOfType_Active_CLKPIN=447
  • NumNodesOfType_Active_CNTRLPIN=441
  • NumNodesOfType_Active_DOUBLE=4953
  • NumNodesOfType_Active_DUMMY=4316
  • NumNodesOfType_Active_DUMMYBANK=218
  • NumNodesOfType_Active_DUMMYESC=45
  • NumNodesOfType_Active_GLOBAL=184
  • NumNodesOfType_Active_HFULLHEX=73
  • NumNodesOfType_Active_HLONG=11
  • NumNodesOfType_Active_HUNIHEX=351
  • NumNodesOfType_Active_INPUT=5227
  • NumNodesOfType_Active_IOBOUTPUT=44
  • NumNodesOfType_Active_OMUX=1346
  • NumNodesOfType_Active_OUTPUT=1386
  • NumNodesOfType_Active_PREBXBY=1508
  • NumNodesOfType_Active_VFULLHEX=228
  • NumNodesOfType_Active_VLONG=39
  • NumNodesOfType_Active_VUNIHEX=465
  • NumNodesOfType_Gnd_BRAMADDR=4
  • NumNodesOfType_Gnd_BRAMDUMMY=77
  • NumNodesOfType_Gnd_CLKPIN=2
  • NumNodesOfType_Gnd_CNTRLPIN=5
  • NumNodesOfType_Gnd_DOUBLE=43
  • NumNodesOfType_Gnd_DUMMY=20
  • NumNodesOfType_Gnd_DUMMYBANK=10
  • NumNodesOfType_Gnd_INPUT=111
  • NumNodesOfType_Gnd_OMUX=44
  • NumNodesOfType_Gnd_OUTPUT=28
  • NumNodesOfType_Gnd_PREBXBY=5
  • NumNodesOfType_Gnd_VFULLHEX=7
  • NumNodesOfType_Vcc_BRAMDUMMY=27
  • NumNodesOfType_Vcc_CNTRLPIN=7
  • NumNodesOfType_Vcc_INPUT=33
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=24
 SiteStatistics
  • IBUF-DIFFMLR=6
  • IBUF-DIFFMTB=9
  • IBUF-DIFFSLR=10
  • IBUF-DIFFSTB=9
  • IOB-DIFFMLR=24
  • IOB-DIFFMTB=19
  • IOB-DIFFSLR=17
  • IOB-DIFFSTB=18
  • SLICEL-SLICEM=328
 		SiteSummary
  • BUFGMUX=6
  • BUFGMUX_GCLKMUX=6
  • BUFGMUX_GCLK_BUFFER=6
  • DCM=2
  • DCM_DCM=2
  • IBUF=36
  • IBUF_DELAY_ADJ_BBOX=36
  • IBUF_INBUF=36
  • IBUF_PAD=36
  • IOB=78
  • IOB_DELAY_ADJ_BBOX=16
  • IOB_INBUF=16
  • IOB_OUTBUF=78
  • IOB_PAD=78
  • RAMB16BWE=12
  • RAMB16BWE_RAMB16BWE=12
  • SLICEL=713
  • SLICEL_C1VDD=6
  • SLICEL_C2VDD=7
  • SLICEL_CYMUXF=34
  • SLICEL_CYMUXG=29
  • SLICEL_F=553
  • SLICEL_F5MUX=114
  • SLICEL_F6MUX=6
  • SLICEL_FFX=276
  • SLICEL_FFY=244
  • SLICEL_G=547
  • SLICEL_GNDF=17
  • SLICEL_GNDG=14
  • SLICEL_XORF=22
  • SLICEL_XORG=22
  • SLICEM=80
  • SLICEM_F=78
  • SLICEM_FFY=2
  • SLICEM_G=80
  • SLICEM_WSGEN=80
 
Configuration Data
BUFGMUX
  • S=[S_INV:6] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:6]
  • S=[S_INV:6] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2:1] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:36]
  • IBUF_DELAY_VALUE=[DLY0:36]
  • IFD_DELAY_VALUE=[DLY0:36]
  • SEL_IN=[SEL_IN:36] [SEL_IN_INV:0]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:36]
 IOB
  • O1=[O1_INV:1] [O1:77]
  • T1=[T1_INV:0] [T1:16]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:16]
  • IBUF_DELAY_VALUE=[DLY0:16]
  • IFD_DELAY_VALUE=[DLY0:16]
  • SEL_IN=[SEL_IN:16] [SEL_IN_INV:0]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:77]
  • SUSPEND=[3STATE:78]
  • TRI=[TRI_INV:0] [TRI:16]
 IOB_PAD
  • DRIVEATTRBOX=[12:68] [24:10]
  • IOATTRBOX=[LVTTL:78]
  • SLEW=[SLOW:78]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:12]
  • CLKB=[CLKB_INV:0] [CLKB:11]
  • ENA=[ENA_INV:0] [ENA:12]
  • ENB=[ENB_INV:0] [ENB:11]
  • SSRA=[SSRA_INV:0] [SSRA:12]
  • SSRB=[SSRB_INV:0] [SSRB:11]
  • WEA0=[WEA0:12] [WEA0_INV:0]
  • WEA1=[WEA1:12] [WEA1_INV:0]
  • WEA2=[WEA2:12] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:12]
  • WEB0=[WEB0:11] [WEB0_INV:1]
  • WEB1=[WEB1:11] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:11]
  • WEB3=[WEB3:11] [WEB3_INV:1]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:12]
  • CLKB=[CLKB_INV:0] [CLKB:11]
  • DATA_WIDTH_A=[1:8] [4:2] [9:1] [18:1]
  • DATA_WIDTH_B=[0:1] [1:8] [4:2] [18:1]
  • ENA=[ENA_INV:0] [ENA:12]
  • ENB=[ENB_INV:0] [ENB:11]
  • SSRA=[SSRA_INV:0] [SSRA:12]
  • SSRB=[SSRB_INV:0] [SSRB:11]
  • WEA0=[WEA0:12] [WEA0_INV:0]
  • WEA1=[WEA1:12] [WEA1_INV:0]
  • WEA2=[WEA2:12] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:12]
  • WEB0=[WEB0:11] [WEB0_INV:1]
  • WEB1=[WEB1:11] [WEB1_INV:1]
  • WEB2=[WEB2_INV:1] [WEB2:11]
  • WEB3=[WEB3:11] [WEB3_INV:1]
  • WRITE_MODE_A=[WRITE_FIRST:12]
  • WRITE_MODE_B=[WRITE_FIRST:12]
 SLICEL
  • BX=[BX_INV:4] [BX:219]
  • BY=[BY:141] [BY_INV:5]
  • CE=[CE:253] [CE_INV:10]
  • CIN=[CIN_INV:0] [CIN:27]
  • CLK=[CLK:243] [CLK_INV:97]
  • SR=[SR:41] [SR_INV:40]
 SLICEL_CYMUXF
  • 0=[0:34] [0_INV:0]
  • 1=[1_INV:0] [1:34]
 SLICEL_CYMUXG
  • 0=[0:29] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:114] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:6] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:216] [CE_INV:8]
  • CK=[CK:190] [CK_INV:86]
  • D=[D:272] [D_INV:4]
  • FFX_INIT_ATTR=[INIT0:268] [INIT1:8]
  • FFX_SR_ATTR=[SRLOW:265] [SRHIGH:11]
  • LATCH_OR_FF=[FF:276]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:34] [SR_INV:26]
  • SYNC_ATTR=[ASYNC:216] [SYNC:60]
 SLICEL_FFY
  • CE=[CE:169] [CE_INV:5]
  • CK=[CK:180] [CK_INV:64]
  • D=[D:239] [D_INV:5]
  • FFY_INIT_ATTR=[INIT0:229] [INIT1:15]
  • FFY_SR_ATTR=[SRLOW:229] [SRHIGH:15]
  • LATCH_OR_FF=[FF:244]
  • SR=[SR:29] [SR_INV:40]
  • SYNC_ATTR=[ASYNC:175] [SYNC:69]
 SLICEL_XORF
  • 1=[1_INV:0] [1:22]
 SLICEM
  • BY=[BY:80] [BY_INV:0]
  • CE=[CE:1] [CE_INV:0]
  • CLK=[CLK:80] [CLK_INV:0]
  • SR=[SR:80] [SR_INV:0]
 SLICEM_F
  • DI=[DI:78] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:78]
  • LUT_OR_MEM=[RAM:78]
 SLICEM_FFY
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:1] [INIT1:1]
  • FFY_SR_ATTR=[SRLOW:2]
  • LATCH_OR_FF=[FF:2]
  • SYNC_ATTR=[ASYNC:2]
 SLICEM_G
  • DI=[DI:80] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:78] [SHIFT_REG:2]
  • LUT_OR_MEM=[RAM:80]
 SLICEM_WSGEN
  • CK=[CK:80] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:2]
  • WE=[WE_INV:0] [WE:80]
 
Pin Data
BUFGMUX
  • I0=6
  • O=6
  • S=6
 BUFGMUX_GCLKMUX
  • I0=6
  • OUT=6
  • S=6
 BUFGMUX_GCLK_BUFFER
  • IN=6
  • OUT=6
 DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=1
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=1
 DCM_DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=1
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=1
 IBUF
  • I=36
  • PAD=36
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=36
  • SEL_IN=36
 IBUF_INBUF
  • IN=36
  • OUT=36
 IBUF_PAD
  • PAD=36
 IOB
  • I=16
  • O1=78
  • PAD=78
  • T1=16
 IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=16
  • SEL_IN=16
 IOB_INBUF
  • IN=16
  • OUT=16
 IOB_OUTBUF
  • IN=78
  • OUT=78
  • TRI=16
 IOB_PAD
  • PAD=78
 RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=12
  • ADDRA11=12
  • ADDRA12=12
  • ADDRA13=12
  • ADDRA2=10
  • ADDRA3=11
  • ADDRA4=12
  • ADDRA5=12
  • ADDRA6=12
  • ADDRA7=12
  • ADDRA8=12
  • ADDRA9=12
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=11
  • ADDRB11=11
  • ADDRB12=11
  • ADDRB13=11
  • ADDRB2=10
  • ADDRB3=10
  • ADDRB4=11
  • ADDRB5=11
  • ADDRB6=11
  • ADDRB7=11
  • ADDRB8=11
  • ADDRB9=11
  • CLKA=12
  • CLKB=11
  • DIA0=11
  • DIA1=3
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=3
  • DIA3=3
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIPA0=1
  • DIPA1=1
  • DOA0=12
  • DOA1=4
  • DOA10=1
  • DOA11=1
  • DOA2=4
  • DOA3=4
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOB0=11
  • DOB1=3
  • DOB10=1
  • DOB11=1
  • DOB2=3
  • DOB3=3
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=12
  • ENB=11
  • SSRA=12
  • SSRB=11
  • WEA0=12
  • WEA1=12
  • WEA2=12
  • WEA3=12
  • WEB0=12
  • WEB1=12
  • WEB2=12
  • WEB3=12
 RAMB16BWE_RAMB16BWE
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=12
  • ADDRA11=12
  • ADDRA12=12
  • ADDRA13=12
  • ADDRA2=10
  • ADDRA3=11
  • ADDRA4=12
  • ADDRA5=12
  • ADDRA6=12
  • ADDRA7=12
  • ADDRA8=12
  • ADDRA9=12
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=11
  • ADDRB11=11
  • ADDRB12=11
  • ADDRB13=11
  • ADDRB2=10
  • ADDRB3=10
  • ADDRB4=11
  • ADDRB5=11
  • ADDRB6=11
  • ADDRB7=11
  • ADDRB8=11
  • ADDRB9=11
  • CLKA=12
  • CLKB=11
  • DIA0=11
  • DIA1=3
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=3
  • DIA3=3
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIPA0=1
  • DIPA1=1
  • DOA0=12
  • DOA1=4
  • DOA10=1
  • DOA11=1
  • DOA2=4
  • DOA3=4
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOB0=11
  • DOB1=3
  • DOB10=1
  • DOB11=1
  • DOB2=3
  • DOB3=3
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=12
  • ENB=11
  • SSRA=12
  • SSRB=11
  • WEA0=12
  • WEA1=12
  • WEA2=12
  • WEA3=12
  • WEB0=12
  • WEB1=12
  • WEB2=12
  • WEB3=12
 SLICEL
  • BX=223
  • BY=146
  • CE=263
  • CIN=27
  • CLK=340
  • COUT=29
  • F1=545
  • F2=497
  • F3=437
  • F4=352
  • F5=12
  • FXINA=6
  • FXINB=6
  • G1=543
  • G2=517
  • G3=441
  • G4=356
  • SR=81
  • X=365
  • XB=1
  • XQ=276
  • Y=328
  • YQ=244
 SLICEL_C1VDD
  • 1=6
 SLICEL_C2VDD
  • 1=7
 SLICEL_CYMUXF
  • 0=34
  • 1=34
  • OUT=34
  • S0=34
 SLICEL_CYMUXG
  • 0=29
  • 1=29
  • OUT=29
  • S0=29
 SLICEL_F
  • A1=545
  • A2=497
  • A3=437
  • A4=352
  • D=553
 SLICEL_F5MUX
  • F=114
  • G=114
  • OUT=114
  • S0=114
 SLICEL_F6MUX
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
 SLICEL_FFX
  • CE=224
  • CK=276
  • D=276
  • Q=276
  • REV=1
  • SR=60
 SLICEL_FFY
  • CE=174
  • CK=244
  • D=244
  • Q=244
  • SR=69
 SLICEL_G
  • A1=543
  • A2=517
  • A3=441
  • A4=356
  • D=547
 SLICEL_GNDF
  • 0=17
 SLICEL_GNDG
  • 0=14
 SLICEL_XORF
  • 0=22
  • 1=22
  • O=22
 SLICEL_XORG
  • 0=22
  • 1=22
  • O=22
 SLICEM
  • BY=80
  • CE=1
  • CLK=80
  • F1=78
  • F2=78
  • F3=78
  • F4=78
  • G1=80
  • G2=80
  • G3=80
  • G4=80
  • SR=80
  • X=78
  • YQ=2
 SLICEM_F
  • A1=78
  • A2=78
  • A3=78
  • A4=78
  • D=78
  • DI=78
  • WF1=78
  • WF2=78
  • WF3=78
  • WF4=78
  • WS=78
 SLICEM_FFY
  • CE=1
  • CK=2
  • D=2
  • Q=2
 SLICEM_G
  • A1=80
  • A2=80
  • A3=80
  • A4=80
  • D=2
  • DI=80
  • WG1=78
  • WG2=78
  • WG3=78
  • WG4=78
  • WS=80
 SLICEM_WSGEN
  • CK=80
  • WE=80
  • WSF=78
  • WSG=80
 
Software Quality
Run Statistics
Bitgen 12923 12922 0 0 0 0 0
MAP 7047 6849 0 0 0 0 0
NGDBuild 7364 7348 0 0 0 0 0
PAR 6841 6489 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74929 74925 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6495 6491 0 0 0 0 0
xst 7099 6996 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=46 NGDBUILD_NUM_FDC=1
NGDBUILD_NUM_FDE=197 NGDBUILD_NUM_FDE_1=148 NGDBUILD_NUM_FDR=60 NGDBUILD_NUM_FDRE=41
NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDR_1=1 NGDBUILD_NUM_FDS=13 NGDBUILD_NUM_FDSE=13
NGDBUILD_NUM_FD_1=1 NGDBUILD_NUM_GND=7 NGDBUILD_NUM_IBUF=23 NGDBUILD_NUM_IBUFG=5
NGDBUILD_NUM_INV=18 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT1=32 NGDBUILD_NUM_LUT2=134
NGDBUILD_NUM_LUT2_D=1 NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=202 NGDBUILD_NUM_LUT3_D=5
NGDBUILD_NUM_LUT4=646 NGDBUILD_NUM_LUT4_D=8 NGDBUILD_NUM_LUT4_L=16 NGDBUILD_NUM_MUXCY=63
NGDBUILD_NUM_MUXF5=114 NGDBUILD_NUM_MUXF6=6 NGDBUILD_NUM_NAND2=1 NGDBUILD_NUM_OBUF=62
NGDBUILD_NUM_OBUFT=3 NGDBUILD_NUM_RAM16X1D=78 NGDBUILD_NUM_SRL16=1 NGDBUILD_NUM_SRLC16E=1
NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=44
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=46 NGDBUILD_NUM_FDC=1
NGDBUILD_NUM_FDE=197 NGDBUILD_NUM_FDE_1=148 NGDBUILD_NUM_FDR=60 NGDBUILD_NUM_FDRE=41
NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDR_1=1 NGDBUILD_NUM_FDS=13 NGDBUILD_NUM_FDSE=13
NGDBUILD_NUM_FD_1=1 NGDBUILD_NUM_GND=11 NGDBUILD_NUM_IBUF=47 NGDBUILD_NUM_IBUFG=5
NGDBUILD_NUM_INV=18 NGDBUILD_NUM_LUT1=32 NGDBUILD_NUM_LUT2=134 NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=202 NGDBUILD_NUM_LUT3_D=5 NGDBUILD_NUM_LUT4=646
NGDBUILD_NUM_LUT4_D=8 NGDBUILD_NUM_LUT4_L=16 NGDBUILD_NUM_MUXCY=63 NGDBUILD_NUM_MUXF5=114
NGDBUILD_NUM_MUXF6=6 NGDBUILD_NUM_NAND2=1 NGDBUILD_NUM_OBUF=62 NGDBUILD_NUM_OBUFT=19
NGDBUILD_NUM_RAMB16BWE=12 NGDBUILD_NUM_SRLC16E=2 NGDBUILD_NUM_VCC=7 NGDBUILD_NUM_XORCY=44