Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.def4846622c0434d9c6d6a2cfeb80550.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-12T21:23:59 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=86
  • AGG_IO=86
  • AGG_SLICE=3435
  • NUM_4_INPUT_LUT=6091
  • NUM_BONDED_IBUF=49
  • NUM_BONDED_IOB=37
  • NUM_BUFGMUX=7
  • NUM_CARRY_SKIP=6
  • NUM_CYMUX=741
  • NUM_DCM=2
  • NUM_DP_RAM=128
  • NUM_IOB_FF=10
  • NUM_LUT_RT=196
  • NUM_MULT18X18SIO=2
  • NUM_RAMB16BWE=19
  • NUM_SHIFT=10
  • NUM_SLICEL=3331
  • NUM_SLICEM=104
  • NUM_SLICE_FF=1830
  • NUM_XOR=637
 		NetStatistics
  • NumNets_Active=6740
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=226
  • NumNodesOfType_Active_BRAMDUMMY=296
  • NumNodesOfType_Active_CLKPIN=1267
  • NumNodesOfType_Active_CNTRLPIN=1891
  • NumNodesOfType_Active_DOUBLE=17100
  • NumNodesOfType_Active_DUMMY=19570
  • NumNodesOfType_Active_DUMMYBANK=237
  • NumNodesOfType_Active_DUMMYESC=24
  • NumNodesOfType_Active_GLOBAL=284
  • NumNodesOfType_Active_HFULLHEX=272
  • NumNodesOfType_Active_HLONG=56
  • NumNodesOfType_Active_HUNIHEX=1640
  • NumNodesOfType_Active_INPUT=21562
  • NumNodesOfType_Active_IOBOUTPUT=31
  • NumNodesOfType_Active_OMUX=6297
  • NumNodesOfType_Active_OUTPUT=6615
  • NumNodesOfType_Active_PREBXBY=4937
  • NumNodesOfType_Active_VFULLHEX=884
  • NumNodesOfType_Active_VLONG=155
  • NumNodesOfType_Active_VUNIHEX=1191
  • NumNodesOfType_Vcc_BRAMDUMMY=83
  • NumNodesOfType_Vcc_CNTRLPIN=7
  • NumNodesOfType_Vcc_DUMMY=10
  • NumNodesOfType_Vcc_INPUT=145
  • NumNodesOfType_Vcc_PREBXBY=48
  • NumNodesOfType_Vcc_VCCOUT=132
 SiteStatistics
  • IBUF-DIFFMLR=12
  • IBUF-DIFFMTB=12
  • IBUF-DIFFSLR=11
  • IBUF-DIFFSTB=12
  • IOB-DIFFMLR=3
  • IOB-DIFFMTB=15
  • IOB-DIFFSLR=4
  • IOB-DIFFSTB=15
  • SLICEL-SLICEM=1612
 		SiteSummary
  • BUFGMUX=7
  • BUFGMUX_GCLKMUX=7
  • BUFGMUX_GCLK_BUFFER=7
  • DCM=2
  • DCM_DCM=2
  • IBUF=49
  • IBUF_DELAY_ADJ_BBOX=49
  • IBUF_IFF1=8
  • IBUF_INBUF=49
  • IBUF_PAD=49
  • IOB=37
  • IOB_OFF1=2
  • IOB_OUTBUF=37
  • IOB_PAD=37
  • MULT18X18SIO=2
  • MULT18X18SIO_MULT18X18SIO=2
  • RAMB16BWE=19
  • RAMB16BWE_RAMB16BWE=19
  • SLICEL=3331
  • SLICEL_C1VDD=60
  • SLICEL_C2VDD=68
  • SLICEL_CYMUXF=390
  • SLICEL_CYMUXG=351
  • SLICEL_F=2961
  • SLICEL_F5MUX=507
  • SLICEL_F6MUX=18
  • SLICEL_FFX=974
  • SLICEL_FFY=814
  • SLICEL_G=2928
  • SLICEL_GNDF=189
  • SLICEL_GNDG=148
  • SLICEL_VDDG=6
  • SLICEL_XORF=327
  • SLICEL_XORG=310
  • SLICEM=104
  • SLICEM_F=98
  • SLICEM_F5MUX=32
  • SLICEM_F6MUX=32
  • SLICEM_FFX=2
  • SLICEM_FFY=40
  • SLICEM_G=104
  • SLICEM_WSGEN=72
 
Configuration Data
BUFGMUX
  • S=[S_INV:7] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:7]
  • S=[S_INV:7] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:1] [RST_INV:1]
 DCM_DCM
  • CLKDV_DIVIDE=[2:1] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:1] [RST_INV:1]
 IBUF
  • ICE=[ICE:8] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:8]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:49]
  • IBUF_DELAY_VALUE=[DLY0:49]
  • IFD_DELAY_VALUE=[DLY0:41] [DLY5:8]
  • SEL_IN=[SEL_IN:49] [SEL_IN_INV:0]
 IBUF_IFF1
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:8] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:8]
  • LATCH_OR_FF=[FF:8]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:49]
 IOB
  • O1=[O1_INV:1] [O1:36]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:2]
 IOB_OFF1
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • LATCH_OR_FF=[FF:2]
  • OFF1_INIT_ATTR=[INIT0:2]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:36]
  • SUSPEND=[3STATE:37]
 IOB_PAD
  • DRIVEATTRBOX=[12:37]
  • IOATTRBOX=[LVTTL:37]
  • SLEW=[SLOW:37]
 MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 MULT18X18SIO_MULT18X18SIO
  • AREG=[0:2]
  • BREG=[0:2]
  • B_INPUT=[DIRECT:2]
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • PREG=[0:2]
  • PREG_CLKINVERSION=[0:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:19]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:19]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:19]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA0=[WEA0:17] [WEA0_INV:2]
  • WEA1=[WEA1:17] [WEA1_INV:2]
  • WEA2=[WEA2:17] [WEA2_INV:2]
  • WEA3=[WEA3_INV:2] [WEA3:17]
  • WEB0=[WEB0:2] [WEB0_INV:17]
  • WEB1=[WEB1:2] [WEB1_INV:17]
  • WEB2=[WEB2_INV:17] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:17]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:19]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[4:8] [9:10] [18:1]
  • DATA_WIDTH_B=[0:17] [9:1] [18:1]
  • ENA=[ENA_INV:0] [ENA:19]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:19]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA0=[WEA0:17] [WEA0_INV:2]
  • WEA1=[WEA1:17] [WEA1_INV:2]
  • WEA2=[WEA2:17] [WEA2_INV:2]
  • WEA3=[WEA3_INV:2] [WEA3:17]
  • WEB0=[WEB0:2] [WEB0_INV:17]
  • WEB1=[WEB1:2] [WEB1_INV:17]
  • WEB2=[WEB2_INV:17] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:17]
  • WRITE_MODE_A=[WRITE_FIRST:19]
  • WRITE_MODE_B=[WRITE_FIRST:19]
 SLICEL
  • BX=[BX_INV:22] [BX:774]
  • BY=[BY:310] [BY_INV:18]
  • CE=[CE:1091] [CE_INV:1]
  • CIN=[CIN_INV:0] [CIN:341]
  • CLK=[CLK:1148] [CLK_INV:12]
  • SR=[SR:655] [SR_INV:22]
 SLICEL_CYMUXF
  • 0=[0:390] [0_INV:0]
  • 1=[1_INV:6] [1:384]
 SLICEL_CYMUXG
  • 0=[0:345] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:507] [S0_INV:0]
 SLICEL_F6MUX
  • S0=[S0:18] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:928] [CE_INV:0]
  • CK=[CK:974] [CK_INV:0]
  • D=[D:958] [D_INV:16]
  • FFX_INIT_ATTR=[INIT0:867] [INIT1:107]
  • FFX_SR_ATTR=[SRLOW:871] [SRHIGH:103]
  • LATCH_OR_FF=[FF:974]
  • REV=[REV_INV:0] [REV:2]
  • SR=[SR:539] [SR_INV:18]
  • SYNC_ATTR=[ASYNC:911] [SYNC:63]
 SLICEL_FFY
  • CE=[CE:759] [CE_INV:1]
  • CK=[CK:802] [CK_INV:12]
  • D=[D:796] [D_INV:18]
  • FFY_INIT_ATTR=[INIT0:759] [INIT1:55]
  • FFY_SR_ATTR=[SRLOW:761] [SRHIGH:53]
  • LATCH_OR_FF=[FF:814]
  • REV=[REV_INV:0] [REV:4]
  • SR=[SR:424] [SR_INV:22]
  • SYNC_ATTR=[ASYNC:730] [SYNC:84]
 SLICEL_XORF
  • 1=[1_INV:6] [1:321]
 SLICEM
  • BX=[BX_INV:0] [BX:34]
  • BY=[BY:104] [BY_INV:0]
  • CE=[CE:40] [CE_INV:0]
  • CLK=[CLK:72] [CLK_INV:0]
  • SR=[SR:72] [SR_INV:0]
 SLICEM_F
  • DI=[DI:66] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:64] [SHIFT_REG:2]
  • LUT_OR_MEM=[LUT:32] [RAM:66]
 SLICEM_F5MUX
  • S0=[S0:32] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:32] [S0_INV:0]
 SLICEM_FFX
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:2]
  • FFX_SR_ATTR=[SRLOW:2]
  • LATCH_OR_FF=[FF:2]
  • SYNC_ATTR=[ASYNC:2]
 SLICEM_FFY
  • CE=[CE:40] [CE_INV:0]
  • CK=[CK:40] [CK_INV:0]
  • D=[D:40] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:40]
  • FFY_SR_ATTR=[SRLOW:40]
  • LATCH_OR_FF=[FF:40]
  • SYNC_ATTR=[ASYNC:40]
 SLICEM_G
  • DI=[DI:72] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:64] [SHIFT_REG:8]
  • LUT_OR_MEM=[LUT:32] [RAM:72]
 SLICEM_WSGEN
  • CK=[CK:72] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:40]
  • WE=[WE_INV:0] [WE:72]
 
Pin Data
BUFGMUX
  • I0=7
  • O=7
  • S=7
 BUFGMUX_GCLKMUX
  • I0=7
  • OUT=7
  • S=7
 BUFGMUX_GCLK_BUFFER
  • IN=7
  • OUT=7
 DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=1
  • CLKIN=2
  • LOCKED=1
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=1
 DCM_DCM
  • CLK0=2
  • CLKDV=1
  • CLKFB=2
  • CLKFX=1
  • CLKIN=2
  • LOCKED=1
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=1
 IBUF
  • I=41
  • ICE=8
  • ICLK1=8
  • IQ1=8
  • PAD=49
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=41
  • IFD_OUT=8
  • SEL_IN=49
 IBUF_IFF1
  • CE=8
  • CK=8
  • D=8
  • Q=8
 IBUF_INBUF
  • IN=49
  • OUT=49
 IBUF_PAD
  • PAD=49
 IOB
  • O1=37
  • OTCLK1=2
  • PAD=37
 IOB_OFF1
  • CK=2
  • D=2
  • Q=2
 IOB_OUTBUF
  • IN=37
  • OUT=37
 IOB_PAD
  • PAD=37
 MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P16=2
  • P17=2
  • P18=2
  • P19=2
  • P20=2
  • P21=2
  • P22=2
  • P23=2
  • P24=2
  • P25=2
  • P26=2
  • P27=2
  • P28=2
  • P29=2
  • P30=2
  • P31=2
  • P32=2
  • P33=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 MULT18X18SIO_MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P16=2
  • P17=2
  • P18=2
  • P19=2
  • P20=2
  • P21=2
  • P22=2
  • P23=2
  • P24=2
  • P25=2
  • P26=2
  • P27=2
  • P28=2
  • P29=2
  • P30=2
  • P31=2
  • P32=2
  • P33=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
 RAMB16BWE
  • ADDRA10=19
  • ADDRA11=19
  • ADDRA12=19
  • ADDRA13=19
  • ADDRA2=8
  • ADDRA3=18
  • ADDRA4=19
  • ADDRA5=19
  • ADDRA6=19
  • ADDRA7=19
  • ADDRA8=19
  • ADDRA9=19
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=1
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=19
  • CLKB=2
  • DIA0=6
  • DIA1=6
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=6
  • DIA3=6
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=1
  • DIA9=1
  • DIPA0=6
  • DIPA1=1
  • DOA0=17
  • DOA1=17
  • DOA2=17
  • DOA3=17
  • DOA4=9
  • DOA5=9
  • DOA6=9
  • DOA7=9
  • DOB0=2
  • DOB1=2
  • DOB10=1
  • DOB11=1
  • DOB2=2
  • DOB3=2
  • DOB4=2
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=19
  • ENB=2
  • SSRA=19
  • SSRB=2
  • WEA0=19
  • WEA1=19
  • WEA2=19
  • WEA3=19
  • WEB0=19
  • WEB1=19
  • WEB2=19
  • WEB3=19
 RAMB16BWE_RAMB16BWE
  • ADDRA10=19
  • ADDRA11=19
  • ADDRA12=19
  • ADDRA13=19
  • ADDRA2=8
  • ADDRA3=18
  • ADDRA4=19
  • ADDRA5=19
  • ADDRA6=19
  • ADDRA7=19
  • ADDRA8=19
  • ADDRA9=19
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB3=1
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=19
  • CLKB=2
  • DIA0=6
  • DIA1=6
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=6
  • DIA3=6
  • DIA4=6
  • DIA5=6
  • DIA6=6
  • DIA7=6
  • DIA8=1
  • DIA9=1
  • DIPA0=6
  • DIPA1=1
  • DOA0=17
  • DOA1=17
  • DOA2=17
  • DOA3=17
  • DOA4=9
  • DOA5=9
  • DOA6=9
  • DOA7=9
  • DOB0=2
  • DOB1=2
  • DOB10=1
  • DOB11=1
  • DOB2=2
  • DOB3=2
  • DOB4=2
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=19
  • ENB=2
  • SSRA=19
  • SSRB=2
  • WEA0=19
  • WEA1=19
  • WEA2=19
  • WEA3=19
  • WEB0=19
  • WEB1=19
  • WEB2=19
  • WEB3=19
 SLICEL
  • BX=796
  • BY=328
  • CE=1092
  • CIN=341
  • CLK=1160
  • COUT=351
  • F1=2947
  • F2=2760
  • F3=2256
  • F4=1633
  • F5=36
  • FX=16
  • FXINA=18
  • FXINB=18
  • G1=2913
  • G2=2734
  • G3=2204
  • G4=1489
  • SR=677
  • X=2140
  • XB=10
  • XQ=974
  • Y=1892
  • YQ=814
 SLICEL_C1VDD
  • 1=60
 SLICEL_C2VDD
  • 1=68
 SLICEL_CYMUXF
  • 0=390
  • 1=390
  • OUT=390
  • S0=390
 SLICEL_CYMUXG
  • 0=345
  • 1=351
  • OUT=351
  • S0=351
 SLICEL_F
  • A1=2944
  • A2=2760
  • A3=2256
  • A4=1633
  • D=2961
 SLICEL_F5MUX
  • F=507
  • G=507
  • OUT=507
  • S0=507
 SLICEL_F6MUX
  • 0=18
  • 1=18
  • OUT=18
  • S0=18
 SLICEL_FFX
  • CE=928
  • CK=974
  • D=974
  • Q=974
  • REV=2
  • SR=557
 SLICEL_FFY
  • CE=760
  • CK=814
  • D=814
  • Q=814
  • REV=4
  • SR=446
 SLICEL_G
  • A1=2910
  • A2=2734
  • A3=2204
  • A4=1489
  • D=2928
 SLICEL_GNDF
  • 0=189
 SLICEL_GNDG
  • 0=148
 SLICEL_VDDG
  • 1=6
 SLICEL_XORF
  • 0=327
  • 1=327
  • O=327
 SLICEL_XORG
  • 0=310
  • 1=310
  • O=310
 SLICEM
  • BX=34
  • BY=104
  • CE=40
  • CLK=72
  • F1=98
  • F2=98
  • F3=98
  • F4=76
  • F5=32
  • FX=16
  • FXINA=32
  • FXINB=32
  • G1=104
  • G2=104
  • G3=104
  • G4=94
  • SR=72
  • X=64
  • XQ=2
  • Y=48
  • YQ=40
 SLICEM_F
  • A1=98
  • A2=98
  • A3=98
  • A4=76
  • D=98
  • DI=66
  • WF1=64
  • WF2=64
  • WF3=64
  • WF4=64
  • WS=66
 SLICEM_F5MUX
  • F=32
  • G=32
  • OUT=32
  • S0=32
 SLICEM_F6MUX
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEM_FFX
  • CE=2
  • CK=2
  • D=2
  • Q=2
 SLICEM_FFY
  • CE=40
  • CK=40
  • D=40
  • Q=40
 SLICEM_G
  • A1=104
  • A2=104
  • A3=104
  • A4=94
  • D=72
  • DI=72
  • WG1=64
  • WG2=64
  • WG3=64
  • WG4=64
  • WS=72
 SLICEM_WSGEN
  • CK=72
  • WE=72
  • WSF=66
  • WSG=72
 
Software Quality
Run Statistics
Bitgen 12985 12984 0 0 0 0 0
MAP 7079 6881 0 0 0 0 0
NGDBuild 7397 7381 0 0 0 0 0
PAR 6873 6520 323 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 75120 75116 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6526 6522 0 0 0 0 0
xst 7162 7059 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_BUF=13 NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_BUFGP=2
NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=34 NGDBUILD_NUM_FDC=31
NGDBUILD_NUM_FDCE=685 NGDBUILD_NUM_FDCPE=6 NGDBUILD_NUM_FDE=794 NGDBUILD_NUM_FDP=2
NGDBUILD_NUM_FDPE=132 NGDBUILD_NUM_FDR=3 NGDBUILD_NUM_FDRE=110 NGDBUILD_NUM_FDR_1=12
NGDBUILD_NUM_FDS=11 NGDBUILD_NUM_FDSE=11 NGDBUILD_NUM_GND=43 NGDBUILD_NUM_IBUF=28
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=218 NGDBUILD_NUM_LUT1=163 NGDBUILD_NUM_LUT2=891
NGDBUILD_NUM_LUT2_D=44 NGDBUILD_NUM_LUT2_L=38 NGDBUILD_NUM_LUT3=1307 NGDBUILD_NUM_LUT3_D=104
NGDBUILD_NUM_LUT3_L=74 NGDBUILD_NUM_LUT4=2677 NGDBUILD_NUM_LUT4_D=137 NGDBUILD_NUM_LUT4_L=303
NGDBUILD_NUM_MULT18X18SIO=2 NGDBUILD_NUM_MUXCY=720 NGDBUILD_NUM_MUXF5=539 NGDBUILD_NUM_MUXF6=34
NGDBUILD_NUM_MUXF7=16 NGDBUILD_NUM_OBUF=37 NGDBUILD_NUM_RAM16X1D=64 NGDBUILD_NUM_RAMB16BWE=19
NGDBUILD_NUM_SRLC16E=10 NGDBUILD_NUM_VCC=29 NGDBUILD_NUM_XORCY=628
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_BUF=13 NGDBUILD_NUM_BUFG=7 NGDBUILD_NUM_DCM_SP=2
NGDBUILD_NUM_FD=43 NGDBUILD_NUM_FDC=31 NGDBUILD_NUM_FDCE=685 NGDBUILD_NUM_FDCPE=6
NGDBUILD_NUM_FDE=794 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=132 NGDBUILD_NUM_FDR=3
NGDBUILD_NUM_FDRE=110 NGDBUILD_NUM_FDR_1=12 NGDBUILD_NUM_FDS=11 NGDBUILD_NUM_FDSE=11
NGDBUILD_NUM_GND=44 NGDBUILD_NUM_IBUF=46 NGDBUILD_NUM_IBUFG=3 NGDBUILD_NUM_INV=219
NGDBUILD_NUM_LUT1=163 NGDBUILD_NUM_LUT1_L=8 NGDBUILD_NUM_LUT2=899 NGDBUILD_NUM_LUT2_D=44
NGDBUILD_NUM_LUT2_L=38 NGDBUILD_NUM_LUT3=1307 NGDBUILD_NUM_LUT3_D=104 NGDBUILD_NUM_LUT3_L=74
NGDBUILD_NUM_LUT4=2681 NGDBUILD_NUM_LUT4_D=137 NGDBUILD_NUM_LUT4_L=304 NGDBUILD_NUM_MULT18X18SIO=2
NGDBUILD_NUM_MUXCY=721 NGDBUILD_NUM_MUXCY_L=14 NGDBUILD_NUM_MUXF5=539 NGDBUILD_NUM_MUXF6=34
NGDBUILD_NUM_MUXF7=16 NGDBUILD_NUM_OBUF=37 NGDBUILD_NUM_RAMB16BWE=19 NGDBUILD_NUM_SRLC16E=10
NGDBUILD_NUM_VCC=29 NGDBUILD_NUM_XORCY=636