Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.f852182198f04be3a34446432a8501bd.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T16:33:23 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=44
  • AGG_IO=44
  • AGG_SLICE=517
  • NUM_4_INPUT_LUT=763
  • NUM_BONDED_IBUF=8
  • NUM_BONDED_IOB=36
  • NUM_BUFGMUX=5
  • NUM_CYMUX=279
  • NUM_DCM=2
  • NUM_IOB_FF=25
  • NUM_LUT_RT=125
  • NUM_MULT18X18SIO=4
  • NUM_ODDR2_NONE=1
  • NUM_RAMB16BWE=3
  • NUM_SHIFT=1
  • NUM_SLICEL=516
  • NUM_SLICEM=1
  • NUM_SLICE_FF=521
  • NUM_XOR=202
 		NetStatistics
  • NumNets_Active=1090
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=66
  • NumNodesOfType_Active_BRAMDUMMY=170
  • NumNodesOfType_Active_CLKPIN=351
  • NumNodesOfType_Active_CNTRLPIN=362
  • NumNodesOfType_Active_DOUBLE=1863
  • NumNodesOfType_Active_DUMMY=1934
  • NumNodesOfType_Active_DUMMYBANK=69
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_GLOBAL=66
  • NumNodesOfType_Active_HFULLHEX=20
  • NumNodesOfType_Active_HLONG=6
  • NumNodesOfType_Active_HUNIHEX=50
  • NumNodesOfType_Active_INPUT=2487
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_OMUX=1118
  • NumNodesOfType_Active_OUTPUT=1046
  • NumNodesOfType_Active_PREBXBY=655
  • NumNodesOfType_Active_VFULLHEX=159
  • NumNodesOfType_Active_VLONG=49
  • NumNodesOfType_Active_VUNIHEX=197
  • NumNodesOfType_Gnd_BRAMDUMMY=103
  • NumNodesOfType_Gnd_CLKPIN=6
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_DOUBLE=29
  • NumNodesOfType_Gnd_DUMMYBANK=24
  • NumNodesOfType_Gnd_INPUT=114
  • NumNodesOfType_Gnd_OMUX=30
  • NumNodesOfType_Gnd_OUTPUT=13
  • NumNodesOfType_Gnd_PREBXBY=7
  • NumNodesOfType_Gnd_VFULLHEX=10
  • NumNodesOfType_Gnd_VLONG=1
  • NumNodesOfType_Vcc_BRAMDUMMY=20
  • NumNodesOfType_Vcc_CNTRLPIN=7
  • NumNodesOfType_Vcc_DUMMY=4
  • NumNodesOfType_Vcc_INPUT=43
  • NumNodesOfType_Vcc_PREBXBY=16
  • NumNodesOfType_Vcc_VCCOUT=33
 SiteStatistics
  • IBUF-DIFFMLR=3
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSI_NDT=1
  • IBUF-DIFFSTB=2
  • IOB-DIFFMLR=3
  • IOB-DIFFMTB=15
  • IOB-DIFFSLR=3
  • IOB-DIFFSTB=15
  • SLICEL-SLICEM=207
 		SiteSummary
  • BUFGMUX=5
  • BUFGMUX_GCLKMUX=5
  • BUFGMUX_GCLK_BUFFER=5
  • DCM=2
  • DCM_DCM=2
  • IBUF=8
  • IBUF_DELAY_ADJ_BBOX=8
  • IBUF_IFF1=1
  • IBUF_INBUF=8
  • IBUF_PAD=8
  • IOB=36
  • IOB_OFF1=25
  • IOB_OFF2=1
  • IOB_OFFDDRBLACKBOX=1
  • IOB_OUTBUF=36
  • IOB_PAD=36
  • MULT18X18SIO=4
  • MULT18X18SIO_MULT18X18SIO=4
  • RAMB16BWE=3
  • RAMB16BWE_RAMB16BWE=3
  • SLICEL=516
  • SLICEL_C1VDD=53
  • SLICEL_C2VDD=51
  • SLICEL_CYMUXF=147
  • SLICEL_CYMUXG=132
  • SLICEL_F=378
  • SLICEL_F5MUX=13
  • SLICEL_FFX=288
  • SLICEL_FFY=233
  • SLICEL_G=384
  • SLICEL_GNDF=94
  • SLICEL_GNDG=81
  • SLICEL_XORF=103
  • SLICEL_XORG=99
  • SLICEM=1
  • SLICEM_G=1
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:5] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:5]
  • S=[S_INV:5] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[4:1] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:2]
  • RST=[RST:2] [RST_INV:0]
 IBUF
  • ICLK1=[ICLK1_INV:0] [ICLK1:1]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:8]
  • IBUF_DELAY_VALUE=[DLY0:8]
  • IFD_DELAY_VALUE=[DLY0:7] [DLY5:1]
  • SEL_IN=[SEL_IN:8] [SEL_IN_INV:0]
 IBUF_IFF1
  • CK=[CK:1] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:1]
  • LATCH_OR_FF=[FF:1]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:8]
 IOB
  • O1=[O1_INV:1] [O1:35]
  • O2=[O2:1] [O2_INV:0]
  • OCE=[OCE:1] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:25]
  • OTCLK2=[OTCLK2_INV:1] [OTCLK2:0]
  • SR=[SR:0] [SR_INV:25]
 IOB_OFF1
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:25] [CK_INV:0]
  • D=[D:25] [D_INV:0]
  • LATCH_OR_FF=[FF:25]
  • OFF1_INIT_ATTR=[INIT0:25]
  • OFF1_SR_ATTR=[SRLOW:25]
  • OFFATTRBOX=[ASYNC:24] [SYNC:1]
  • SR=[SR:0] [SR_INV:25]
 IOB_OFF2
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:0] [CK_INV:1]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF2_INIT_ATTR=[INIT0:1]
  • OFF2_SR_ATTR=[SRLOW:1]
  • OFFATTRBOX=[SYNC:1]
  • SR=[SR:0] [SR_INV:1]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:35]
  • SUSPEND=[3STATE:36]
 IOB_PAD
  • DRIVEATTRBOX=[12:36]
  • IOATTRBOX=[LVTTL:36]
  • SLEW=[SLOW:36]
 MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:4]
  • CEB=[CEB_INV:0] [CEB:4]
  • CEP=[CEP:4] [CEP_INV:0]
  • CLK=[CLK:4] [CLK_INV:0]
  • RSTA=[RSTA:4] [RSTA_INV:0]
  • RSTB=[RSTB:4] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:4]
 MULT18X18SIO_MULT18X18SIO
  • AREG=[0:4]
  • BREG=[0:4]
  • B_INPUT=[DIRECT:4]
  • CEA=[CEA_INV:0] [CEA:4]
  • CEB=[CEB_INV:0] [CEB:4]
  • CEP=[CEP:4] [CEP_INV:0]
  • CLK=[CLK:4] [CLK_INV:0]
  • PREG=[0:4]
  • PREG_CLKINVERSION=[0:4]
  • RSTA=[RSTA:4] [RSTA_INV:0]
  • RSTB=[RSTB:4] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:4]
 RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:3]
  • CLKB=[CLKB_INV:0] [CLKB:3]
  • ENA=[ENA_INV:0] [ENA:3]
  • ENB=[ENB_INV:0] [ENB:3]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • SSRB=[SSRB_INV:0] [SSRB:3]
  • WEA0=[WEA0:3] [WEA0_INV:0]
  • WEA1=[WEA1:3] [WEA1_INV:0]
  • WEA2=[WEA2:3] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:3]
  • WEB0=[WEB0:3] [WEB0_INV:0]
  • WEB1=[WEB1:3] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:3]
  • WEB3=[WEB3:3] [WEB3_INV:0]
 RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:3]
  • CLKB=[CLKB_INV:0] [CLKB:3]
  • DATA_WIDTH_A=[9:3]
  • DATA_WIDTH_B=[9:3]
  • ENA=[ENA_INV:0] [ENA:3]
  • ENB=[ENB_INV:0] [ENB:3]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • SSRB=[SSRB_INV:0] [SSRB:3]
  • WEA0=[WEA0:3] [WEA0_INV:0]
  • WEA1=[WEA1:3] [WEA1_INV:0]
  • WEA2=[WEA2:3] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:3]
  • WEB0=[WEB0:3] [WEB0_INV:0]
  • WEB1=[WEB1:3] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:3]
  • WEB3=[WEB3:3] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:3]
  • WRITE_MODE_B=[WRITE_FIRST:3]
 SLICEL
  • BX=[BX_INV:3] [BX:143]
  • BY=[BY:120] [BY_INV:7]
  • CE=[CE:130] [CE_INV:34]
  • CIN=[CIN_INV:0] [CIN:124]
  • CLK=[CLK:308] [CLK_INV:5]
  • SR=[SR:124] [SR_INV:47]
 SLICEL_CYMUXF
  • 0=[0:147] [0_INV:0]
  • 1=[1_INV:3] [1:144]
 SLICEL_CYMUXG
  • 0=[0:132] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:13] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:122] [CE_INV:32]
  • CK=[CK:284] [CK_INV:4]
  • D=[D:288] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:274] [INIT1:14]
  • FFX_SR_ATTR=[SRLOW:277] [SRHIGH:11]
  • LATCH_OR_FF=[FF:288]
  • REV=[REV_INV:0] [REV:71]
  • SR=[SR:121] [SR_INV:36]
  • SYNC_ATTR=[ASYNC:250] [SYNC:38]
 SLICEL_FFY
  • CE=[CE:126] [CE_INV:32]
  • CK=[CK:228] [CK_INV:5]
  • D=[D:226] [D_INV:7]
  • FFY_INIT_ATTR=[INIT0:221] [INIT1:12]
  • FFY_SR_ATTR=[SRLOW:222] [SRHIGH:11]
  • LATCH_OR_FF=[FF:233]
  • REV=[REV_INV:0] [REV:9]
  • SR=[SR:56] [SR_INV:39]
  • SYNC_ATTR=[ASYNC:196] [SYNC:37]
 SLICEL_XORF
  • 1=[1_INV:3] [1:100]
 SLICEM
  • BY=[BY:1] [BY_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
 SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
 SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=5
  • O=5
  • S=5
 BUFGMUX_GCLKMUX
  • I0=5
  • OUT=5
  • S=5
 BUFGMUX_GCLK_BUFFER
  • IN=5
  • OUT=5
 DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
 DCM_DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
 IBUF
  • I=8
  • ICLK1=1
  • IQ1=1
  • PAD=8
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=8
  • IFD_OUT=1
  • SEL_IN=8
 IBUF_IFF1
  • CK=1
  • D=1
  • Q=1
 IBUF_INBUF
  • IN=8
  • OUT=8
 IBUF_PAD
  • PAD=8
 IOB
  • O1=36
  • O2=1
  • OCE=1
  • OTCLK1=25
  • OTCLK2=1
  • PAD=36
  • SR=25
 IOB_OFF1
  • CE=1
  • CK=25
  • D=25
  • Q=25
  • SR=25
 IOB_OFF2
  • CE=1
  • CK=1
  • D=1
  • Q=1
  • SR=1
 IOB_OFFDDRBLACKBOX
  • OFF1=1
  • OFF2=1
  • OFFDDR=1
 IOB_OUTBUF
  • IN=36
  • OUT=36
 IOB_PAD
  • PAD=36
 MULT18X18SIO
  • A0=4
  • A1=4
  • A10=4
  • A11=4
  • A12=4
  • A13=4
  • A14=4
  • A15=4
  • A16=4
  • A17=4
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • A7=4
  • A8=4
  • A9=4
  • B0=4
  • B1=4
  • B10=4
  • B11=4
  • B12=4
  • B13=4
  • B14=4
  • B15=4
  • B16=4
  • B17=4
  • B2=4
  • B3=4
  • B4=4
  • B5=4
  • B6=4
  • B7=4
  • B8=4
  • B9=4
  • CEA=4
  • CEB=4
  • CEP=4
  • CLK=4
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=4
  • P14=3
  • P15=3
  • P16=3
  • P17=3
  • P18=3
  • P19=3
  • P2=1
  • P20=3
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RSTA=4
  • RSTB=4
  • RSTP=4
 MULT18X18SIO_MULT18X18SIO
  • A0=4
  • A1=4
  • A10=4
  • A11=4
  • A12=4
  • A13=4
  • A14=4
  • A15=4
  • A16=4
  • A17=4
  • A2=4
  • A3=4
  • A4=4
  • A5=4
  • A6=4
  • A7=4
  • A8=4
  • A9=4
  • B0=4
  • B1=4
  • B10=4
  • B11=4
  • B12=4
  • B13=4
  • B14=4
  • B15=4
  • B16=4
  • B17=4
  • B2=4
  • B3=4
  • B4=4
  • B5=4
  • B6=4
  • B7=4
  • B8=4
  • B9=4
  • CEA=4
  • CEB=4
  • CEP=4
  • CLK=4
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=4
  • P14=3
  • P15=3
  • P16=3
  • P17=3
  • P18=3
  • P19=3
  • P2=1
  • P20=3
  • P3=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RSTA=4
  • RSTB=4
  • RSTP=4
 RAMB16BWE
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=3
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • ADDRB10=3
  • ADDRB11=3
  • ADDRB12=3
  • ADDRB13=3
  • ADDRB3=3
  • ADDRB4=3
  • ADDRB5=3
  • ADDRB6=3
  • ADDRB7=3
  • ADDRB8=3
  • ADDRB9=3
  • CLKA=3
  • CLKB=3
  • DIA0=3
  • DIA1=3
  • DIA2=3
  • DIA3=3
  • DIA4=3
  • DIA5=3
  • DIA6=3
  • DIA7=3
  • DIPA0=3
  • DOB0=3
  • DOB1=3
  • DOB2=3
  • DOB3=3
  • DOB4=3
  • DOB5=3
  • DOB6=3
  • DOB7=3
  • ENA=3
  • ENB=3
  • SSRA=3
  • SSRB=3
  • WEA0=3
  • WEA1=3
  • WEA2=3
  • WEA3=3
  • WEB0=3
  • WEB1=3
  • WEB2=3
  • WEB3=3
 RAMB16BWE_RAMB16BWE
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=3
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • ADDRB10=3
  • ADDRB11=3
  • ADDRB12=3
  • ADDRB13=3
  • ADDRB3=3
  • ADDRB4=3
  • ADDRB5=3
  • ADDRB6=3
  • ADDRB7=3
  • ADDRB8=3
  • ADDRB9=3
  • CLKA=3
  • CLKB=3
  • DIA0=3
  • DIA1=3
  • DIA2=3
  • DIA3=3
  • DIA4=3
  • DIA5=3
  • DIA6=3
  • DIA7=3
  • DIPA0=3
  • DOB0=3
  • DOB1=3
  • DOB2=3
  • DOB3=3
  • DOB4=3
  • DOB5=3
  • DOB6=3
  • DOB7=3
  • ENA=3
  • ENB=3
  • SSRA=3
  • SSRB=3
  • WEA0=3
  • WEA1=3
  • WEA2=3
  • WEA3=3
  • WEB0=3
  • WEB1=3
  • WEB2=3
  • WEB3=3
 SLICEL
  • BX=146
  • BY=127
  • CE=164
  • CIN=124
  • CLK=313
  • COUT=132
  • F1=376
  • F2=304
  • F3=185
  • F4=87
  • G1=382
  • G2=309
  • G3=182
  • G4=78
  • SR=171
  • X=150
  • XB=7
  • XQ=288
  • Y=151
  • YQ=233
 SLICEL_C1VDD
  • 1=53
 SLICEL_C2VDD
  • 1=51
 SLICEL_CYMUXF
  • 0=147
  • 1=147
  • OUT=147
  • S0=147
 SLICEL_CYMUXG
  • 0=132
  • 1=132
  • OUT=132
  • S0=132
 SLICEL_F
  • A1=376
  • A2=304
  • A3=185
  • A4=87
  • D=378
 SLICEL_F5MUX
  • F=13
  • G=13
  • OUT=13
  • S0=13
 SLICEL_FFX
  • CE=154
  • CK=288
  • D=288
  • Q=288
  • REV=71
  • SR=157
 SLICEL_FFY
  • CE=158
  • CK=233
  • D=233
  • Q=233
  • REV=9
  • SR=95
 SLICEL_G
  • A1=382
  • A2=309
  • A3=182
  • A4=78
  • D=384
 SLICEL_GNDF
  • 0=94
 SLICEL_GNDG
  • 0=81
 SLICEL_XORF
  • 0=103
  • 1=103
  • O=103
 SLICEL_XORG
  • 0=99
  • 1=99
  • O=99
 SLICEM
  • BY=1
  • CLK=1
  • G1=1
  • G2=1
  • G3=1
  • G4=1
  • SR=1
  • Y=1
 SLICEM_G
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
 SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSG=1
 
Software Quality
Run Statistics
Bitgen 12853 12852 0 0 0 0 0
MAP 7010 6814 0 0 0 0 0
NGDBuild 7327 7311 0 0 0 0 0
PAR 6806 6454 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74255 74251 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6460 6456 0 0 0 0 0
xst 7080 6978 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=45
NGDBUILD_NUM_FDCE=10 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDR=11 NGDBUILD_NUM_FDRE=31
NGDBUILD_NUM_FDRS=16 NGDBUILD_NUM_FDS=8 NGDBUILD_NUM_FDSE=9 NGDBUILD_NUM_GND=9
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=28 NGDBUILD_NUM_LUT1=58
NGDBUILD_NUM_LUT2=64 NGDBUILD_NUM_LUT3=54 NGDBUILD_NUM_LUT4=123 NGDBUILD_NUM_MULT18X18SIO=4
NGDBUILD_NUM_MUXCY=141 NGDBUILD_NUM_MUXF5=10 NGDBUILD_NUM_OBUF=36 NGDBUILD_NUM_ODDR2=1
NGDBUILD_NUM_RAMB16BWE=3 NGDBUILD_NUM_SRL16=1 NGDBUILD_NUM_VCC=8 NGDBUILD_NUM_XORCY=76
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=67 NGDBUILD_NUM_FDC=55
NGDBUILD_NUM_FDCE=74 NGDBUILD_NUM_FDCE_1=3 NGDBUILD_NUM_FDCP=64 NGDBUILD_NUM_FDC_1=5
NGDBUILD_NUM_FDE=194 NGDBUILD_NUM_FDP=8 NGDBUILD_NUM_FDPE_1=1 NGDBUILD_NUM_FDR=11
NGDBUILD_NUM_FDRE=31 NGDBUILD_NUM_FDRS=16 NGDBUILD_NUM_FDS=8 NGDBUILD_NUM_FDSE=9
NGDBUILD_NUM_GND=13 NGDBUILD_NUM_IBUF=7 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=34
NGDBUILD_NUM_LUT1=58 NGDBUILD_NUM_LUT1_L=66 NGDBUILD_NUM_LUT2=198 NGDBUILD_NUM_LUT2_L=48
NGDBUILD_NUM_LUT3=65 NGDBUILD_NUM_LUT3_L=141 NGDBUILD_NUM_LUT4=152 NGDBUILD_NUM_LUT4_L=8
NGDBUILD_NUM_MULT18X18SIO=4 NGDBUILD_NUM_MUXCY=143 NGDBUILD_NUM_MUXCY_L=136 NGDBUILD_NUM_MUXF5=13
NGDBUILD_NUM_OBUF=36 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_RAMB16BWE=3 NGDBUILD_NUM_SRLC16E=1
NGDBUILD_NUM_VCC=10 NGDBUILD_NUM_XORCY=202